Lines Matching defs:par
23 u8 aty_ld_pll_ct(int offset, const struct atyfb_par *par)
28 aty_st_8(CLOCK_CNTL_ADDR, (offset << 2) & PLL_ADDR, par);
30 res = aty_ld_8(CLOCK_CNTL_DATA, par);
34 static void aty_st_pll_ct(int offset, u8 val, const struct atyfb_par *par)
37 aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) | PLL_WR_EN, par);
39 aty_st_8(CLOCK_CNTL_DATA, val & PLL_DATA, par);
40 aty_st_8(CLOCK_CNTL_ADDR, ((offset << 2) & PLL_ADDR) & ~PLL_WR_EN, par);
143 struct atyfb_par *par = (struct atyfb_par *) info->par;
145 multiplier = multiplier * par->lcd_width;
148 ras_multiplier = ras_multiplier * par->lcd_width;
212 struct atyfb_par *par = (struct atyfb_par *) info->par;
216 q = par->ref_clk_per * pll->pll_ref_div * 4 / vclk_per;
229 (par->ref_clk_per * pll->pll_ref_div);
237 if (par->pll_limits.ecp_max) {
241 while (ecp > par->pll_limits.ecp_max && ecp_div < 2) {
253 struct atyfb_par *par = (struct atyfb_par *) info->par;
266 struct atyfb_par *par = (struct atyfb_par *) info->par;
268 ret = par->ref_clk_per * pll->ct.pll_ref_div * pll->ct.vclk_post_div_real / pll->ct.vclk_fb_div / 2;
271 ret *= par->lcd_width;
283 struct atyfb_par *par = (struct atyfb_par *) info->par;
296 par->clk_wr_offset, pll->ct.vclk_fb_div,
300 if (par->lcd_table != 0) {
302 lcd_gen_cntrl = aty_ld_lcd(LCD_GEN_CNTL, par);
303 aty_st_lcd(LCD_GEN_CNTL, lcd_gen_cntrl & ~LCD_ON, par);
306 aty_st_8(CLOCK_CNTL, par->clk_wr_offset | CLOCK_STROBE, par);
309 crtc_gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
311 aty_st_le32(CRTC_GEN_CNTL, crtc_gen_cntl | CRTC_EXT_DISP_EN, par);
314 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par);
317 tmp2 = par->clk_wr_offset << 1;
318 tmp = aty_ld_pll_ct(VCLK_POST_DIV, par);
321 aty_st_pll_ct(VCLK_POST_DIV, tmp, par);
324 tmp = aty_ld_pll_ct(PLL_EXT_CNTL, par);
325 tmp &= ~(0x10U << par->clk_wr_offset);
328 aty_st_pll_ct(PLL_EXT_CNTL, tmp, par);
331 tmp = VCLK0_FB_DIV + par->clk_wr_offset;
332 aty_st_pll_ct(tmp, (pll->ct.vclk_fb_div & 0xFFU), par);
334 aty_st_pll_ct(PLL_GEN_CNTL, (pll->ct.pll_gen_cntl & (~(PLL_OVERRIDE | PLL_MCLK_RST))) | OSC_EN, par);
337 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl & ~(PLL_VCLK_RST), par);
340 aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par);
341 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par);
346 aty_st_le32(CRTC_GEN_CNTL, crtc_gen_cntl, par);
353 else if (par->ram_type >= SDRAM)
357 aty_st_pll_ct(DLL_CNTL, dll_cntl, par);
358 aty_st_pll_ct(VFC_CNTL, 0x1b, par);
359 aty_st_le32(DSP_CONFIG, pll->ct.dsp_config, par);
360 aty_st_le32(DSP_ON_OFF, pll->ct.dsp_on_off, par);
363 aty_st_pll_ct(DLL_CNTL, dll_cntl, par);
365 aty_st_pll_ct(DLL_CNTL, dll_cntl | 0x40, par);
367 aty_st_pll_ct(DLL_CNTL, dll_cntl & ~0x40, par);
370 if (par->lcd_table != 0) {
372 aty_st_lcd(LCD_GEN_CNTL, lcd_gen_cntrl, par);
379 struct atyfb_par *par = (struct atyfb_par *) info->par;
382 clock = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
384 pll->ct.vclk_post_div = (aty_ld_pll_ct(VCLK_POST_DIV, par) >> tmp) & 0x03U;
386 pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par) & 0x0FU;
387 pll->ct.vclk_fb_div = aty_ld_pll_ct(VCLK0_FB_DIV + clock, par) & 0xFFU;
388 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
389 pll->ct.mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par);
391 pll->ct.pll_gen_cntl = aty_ld_pll_ct(PLL_GEN_CNTL, par);
392 pll->ct.pll_vclk_cntl = aty_ld_pll_ct(PLL_VCLK_CNTL, par);
395 pll->ct.dsp_config = aty_ld_le32(DSP_CONFIG, par);
396 pll->ct.dsp_on_off = aty_ld_le32(DSP_ON_OFF, par);
402 struct atyfb_par *par = (struct atyfb_par *) info->par;
409 pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par);
436 memcntl = aty_ld_le32(MEM_CNTL, par);
450 switch (par->ram_type) {
490 dsp_config = aty_ld_le32(DSP_CONFIG, par);
491 dsp_on_off = aty_ld_le32(DSP_ON_OFF, par);
492 vga_dsp_config = aty_ld_le32(VGA_DSP_CONFIG, par);
493 vga_dsp_on_off = aty_ld_le32(VGA_DSP_ON_OFF, par);
512 if (par->mclk_per == 0) {
514 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
515 pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par);
517 mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par);
524 pll->ct.pll_ref_div = par->pll_per * 2 * 255 / par->ref_clk_per;
527 q = par->ref_clk_per * pll->ct.pll_ref_div * 8 /
528 (pll->ct.mclk_fb_mult * par->xclk_per);
551 (par->ref_clk_per * pll->ct.pll_ref_div);
556 if (M64_HAS(SDRAM_MAGIC_PLL) && (par->ram_type >= SDRAM))
569 if (par->mclk_per == par->xclk_per) {
578 q = par->ref_clk_per * pll->ct.pll_ref_div * 4 / par->mclk_per;
592 (par->ref_clk_per * pll->ct.pll_ref_div);
599 pll->ct.ext_vpll_cntl = aty_ld_pll_ct(EXT_VPLL_CNTL, par);
608 struct atyfb_par *par = info->par;
610 if (par->mclk_per != par->xclk_per) {
618 aty_st_pll_ct(SCLK_FB_DIV, pll->ct.sclk_fb_div, par);
619 aty_st_pll_ct(SPLL_CNTL2, pll->ct.spll_cntl2, par);
627 aty_st_pll_ct(PLL_REF_DIV, pll->ct.pll_ref_div, par);
628 aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par);
629 aty_st_pll_ct(MCLK_FB_DIV, pll->ct.mclk_fb_div, par);
630 aty_st_pll_ct(PLL_EXT_CNTL, pll->ct.pll_ext_cntl, par);
631 aty_st_pll_ct(EXT_VPLL_CNTL, pll->ct.ext_vpll_cntl, par);