Lines Matching defs:clock
48 * ATI Mach64 CT clock synthesis description.
56 * XTALIN is a fixed speed clock. Common speeds are 14.31 MHz and 29.50 MHz.
58 * FB_DIV can be set by the user for each clock individually, it should be set
59 * between 128 and 255, the chip will generate a bad clock signal for too low
61 * x depends on the type of clock; usually it is 2, but for the MCLK it can also
63 * POST_DIV can be set by the user for each clock individually, Possible values
65 * CLK is of course the clock speed that is generated.
69 * MCLK The clock rate of the chip
70 * XCLK The clock rate of the on-chip memory
71 * VCLK0 First pixel clock of first CRT controller
72 * VCLK1 Second pixel clock of first CRT controller
73 * VCLK2 Third pixel clock of first CRT controller
74 * VCLK3 Fourth pixel clock of first CRT controller
75 * VCLK Selected pixel clock, one of VCLK0, VCLK1, VCLK2, VCLK3
76 * V2CLK Pixel clock of the second CRT controller.
77 * SCLK Multi-purpose clock
92 * - Generate the pixel clock for the LCD monitor (instead of VCLK)
97 * same frequency. Luckily, until now all cards that need asynchrone clock
99 * So this driver uses SCLK to clock the chip and XCLK to clock the memory.
236 /* Set ECP (scaler/overlay clock) divider */
294 printk("atyfb(%s): setting clock %lu for FeedBackDivider %i, ReferenceDivider %i, PostDivider %i(%i)\n",
380 u8 tmp, clock;
382 clock = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
383 tmp = clock << 1;
387 pll->ct.vclk_fb_div = aty_ld_pll_ct(VCLK0_FB_DIV + clock, par) & 0xFFU;
510 /* Exit if the user does not want us to tamper with the clock
573 * The chip clock is not equal to the memory clock.
574 * Therefore we will use sclk to clock the chip.
598 /* Disable the extra precision pixel clock controls since we do not use them. */