Lines Matching defs:par
149 void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
152 aty_st_le32(lt_lcd_regs[index], val, par);
157 temp = aty_ld_le32(LCD_INDEX, par);
158 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
160 aty_st_le32(LCD_DATA, val, par);
164 u32 aty_ld_lcd(int index, const struct atyfb_par *par)
167 return aty_ld_le32(lt_lcd_regs[index], par);
172 temp = aty_ld_le32(LCD_INDEX, par);
173 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
175 return aty_ld_le32(LCD_DATA, par);
256 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc);
258 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc);
264 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info);
266 static int read_aty_sense(const struct atyfb_par *par);
436 struct atyfb_par *par = (struct atyfb_par *) info->par;
438 if (!par->aux_start &&
440 (par->bus_type == ISA && info->fix.smem_len == 0x400000)))
444 static int correct_chipset(struct atyfb_par *par)
453 if (par->pci_id == aty_chips[i].pci_id)
460 par->pll_limits.pll_max = aty_chips[i].pll;
461 par->pll_limits.mclk = aty_chips[i].mclk;
462 par->pll_limits.xclk = aty_chips[i].xclk;
463 par->pll_limits.ecp_max = aty_chips[i].ecp_max;
464 par->features = aty_chips[i].features;
466 chip_id = aty_ld_le32(CNFG_CHIP_ID, par);
470 switch (par->pci_id) {
488 par->pll_limits.pll_max = 170;
489 par->pll_limits.mclk = 67;
490 par->pll_limits.xclk = 67;
491 par->pll_limits.ecp_max = 80;
492 par->features = ATI_CHIP_264VT;
496 par->pll_limits.pll_max = 200;
497 par->pll_limits.mclk = 67;
498 par->pll_limits.xclk = 67;
499 par->pll_limits.ecp_max = 80;
500 par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
506 par->pll_limits.pll_max = 200;
507 par->pll_limits.mclk = 67;
508 par->pll_limits.xclk = 67;
509 par->pll_limits.ecp_max = 80;
510 par->features = ATI_CHIP_264VTB;
514 par->pll_limits.pll_max = 200;
515 par->pll_limits.mclk = 67;
516 par->pll_limits.xclk = 67;
517 par->pll_limits.ecp_max = 80;
518 par->features = ATI_CHIP_264VT3;
526 par->pll_limits.pll_max = 170;
527 par->pll_limits.mclk = 67;
528 par->pll_limits.xclk = 67;
529 par->pll_limits.ecp_max = 80;
530 par->features = ATI_CHIP_264GTB;
534 par->pll_limits.pll_max = 200;
535 par->pll_limits.mclk = 67;
536 par->pll_limits.xclk = 67;
537 par->pll_limits.ecp_max = 100;
538 par->features = ATI_CHIP_264GTB;
583 struct atyfb_par *par)
588 par->pll.ct.xres = 0;
589 if (par->lcd_table != 0) {
590 lcd_on_off = aty_ld_lcd(LCD_GEN_CNTL, par);
592 par->pll.ct.xres = var->xres;
593 pixclock = par->lcd_pixclock;
606 static int read_aty_sense(const struct atyfb_par *par)
610 aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */
612 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
614 i = aty_ld_le32(GP_IO, par); /* get primary sense value */
618 aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */
620 i = aty_ld_le32(GP_IO, par);
622 aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */
625 aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */
627 i = aty_ld_le32(GP_IO, par);
629 aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */
632 aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */
634 sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
635 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
647 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc)
650 if (par->lcd_table != 0) {
652 crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
653 aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
655 crtc->lcd_config_panel = aty_ld_lcd(CNFG_PANEL, par);
656 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
661 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
664 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
665 crtc->vert_stretching = aty_ld_lcd(VERT_STRETCHING, par);
667 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par);
670 crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
671 crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
672 crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
673 crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
674 crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par);
675 crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par);
676 crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
679 if (par->lcd_table != 0) {
682 SHADOW_EN | SHADOW_RW_EN, par);
684 crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
685 crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
686 crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
687 crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
689 aty_st_le32(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
694 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc)
697 if (par->lcd_table != 0) {
700 ~(CRTC_EXT_DISP_EN | CRTC_EN), par);
703 aty_st_lcd(CNFG_PANEL, crtc->lcd_config_panel, par);
705 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
709 ~(HORZ_STRETCH_MODE | HORZ_STRETCH_EN), par);
712 VERT_STRETCH_USE0 | VERT_STRETCH_EN), par);
716 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~CRTC_EN, par);
734 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par);
735 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par);
736 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par);
737 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par);
738 aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par);
739 aty_st_le32(CRTC_VLINE_CRNT_VLINE, crtc->vline_crnt_vline, par);
741 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par);
744 if (par->accel_flags & FB_ACCELF_TEXT)
745 aty_init_engine(par, info);
749 if (par->lcd_table != 0) {
752 SHADOW_EN | SHADOW_RW_EN, par);
769 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->shadow_h_tot_disp, par);
770 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->shadow_h_sync_strt_wid, par);
771 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->shadow_v_tot_disp, par);
772 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->shadow_v_sync_strt_wid, par);
781 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
782 aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching, par);
783 aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching, par);
785 aty_st_lcd(EXT_VERT_STRETCH, crtc->ext_vert_stretch, par);
786 aty_ld_le32(LCD_INDEX, par);
787 aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
793 static u32 calc_line_length(struct atyfb_par *par, u32 vxres, u32 bpp)
797 if (par->ram_type == SGRAM ||
798 (!M64_HAS(XL_MEM) && par->ram_type == WRAM))
808 struct atyfb_par *par = (struct atyfb_par *) info->par;
871 line_length = calc_line_length(par, vxres, bpp);
893 if (par->lcd_table != 0) {
895 u32 lcd_index = aty_ld_le32(LCD_INDEX, par);
899 aty_st_le32(LCD_INDEX, lcd_index, par);
905 crtc->lcd_config_panel = aty_ld_lcd(CNFG_PANEL, par) | 0x4000;
906 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
915 ((xres > par->lcd_width) || (yres > par->lcd_height))) {
927 /*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/
936 if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) {
953 if (yres < par->lcd_height) {
954 VScan = par->lcd_height / yres;
961 h_sync_strt = h_disp + par->lcd_right_margin;
962 h_sync_end = h_sync_strt + par->lcd_hsync_len;
963 h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly;
964 h_total = h_disp + par->lcd_hblank_len;
966 v_sync_strt = v_disp + par->lcd_lower_margin / VScan;
967 v_sync_end = v_sync_strt + par->lcd_vsync_len / VScan;
968 v_total = v_disp + par->lcd_vblank_len / VScan;
1026 /* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */
1037 if (par->lcd_table != 0) {
1050 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
1052 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par) &
1058 if (xres < par->lcd_width && crtc->lcd_gen_cntl & LCD_ON) {
1075 int nStretch = par->lcd_width / HDisplay;
1076 int Remainder = par->lcd_width % HDisplay;
1079 (((HDisplay * 16) / par->lcd_width) < 7)) {
1082 int Numerator = HDisplay, Denominator = par->lcd_width;
1120 (((HDisplay * (HORZ_STRETCH_BLEND + 1)) / par->lcd_width) & HORZ_STRETCH_BLEND));
1124 if (vdisplay < par->lcd_height && crtc->lcd_gen_cntl & LCD_ON) {
1126 (((vdisplay * (VERT_STRETCH_RATIO0 + 1)) / par->lcd_height) & VERT_STRETCH_RATIO0));
1148 crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_FIFO_LWM);
1294 struct atyfb_par *par = (struct atyfb_par *) info->par;
1302 if (par->asleep)
1305 err = aty_var_to_crtc(info, var, &par->crtc);
1309 pixclock = atyfb_get_pixclock(var, par);
1315 err = par->pll_ops->var_to_pll(info, pixclock,
1316 var->bits_per_pixel, &par->pll);
1321 par->accel_flags = var->accel_flags; /* hack */
1331 if (par->blitter_may_be_busy)
1332 wait_for_idle(par);
1334 aty_set_crtc(par, &par->crtc);
1335 par->dac_ops->set_dac(info, &par->pll,
1336 var->bits_per_pixel, par->accel_flags);
1337 par->pll_ops->set_pll(info, &par->pll);
1340 if (par->pll_ops && par->pll_ops->pll_to_var)
1341 pixclock_in_ps = par->pll_ops->pll_to_var(info, &par->pll);
1351 if (!aty_crtc_to_var(&par->crtc, &debug)) {
1367 if (par->crtc.gen_cntl & CRTC_INTERLACE_EN)
1369 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1396 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
1408 aty_st_le32(MEM_CNTL, tmp, par);
1410 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
1412 tmp |= par->mem_refresh_rate << 20;
1426 aty_st_le32(DAC_CNTL, 0x87010184, par);
1427 aty_st_le32(BUS_CNTL, 0x680000f9, par);
1429 aty_st_le32(DAC_CNTL, 0x87010184, par);
1430 aty_st_le32(BUS_CNTL, 0x680000f9, par);
1432 aty_st_le32(DAC_CNTL, 0x80010102, par);
1433 aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1436 aty_st_le32(DAC_CNTL, 0x86010102, par);
1437 aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1438 aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par);
1440 aty_st_le32(MEM_CNTL, tmp, par);
1442 aty_st_8(DAC_MASK, 0xff, par);
1444 info->fix.line_length = calc_line_length(par, var->xres_virtual,
1451 if (par->accel_flags & FB_ACCELF_TEXT)
1452 aty_init_engine(par, info);
1456 (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8,
1457 ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1,
1459 par->crtc.vxres * var->bits_per_pixel / 8);
1474 pr_cont(" %08X", aty_ld_le32(i, par));
1489 pr_cont("%02X", aty_ld_pll_ct(i, par));
1495 if (par->lcd_table != 0) {
1505 pr_cont(" %08X", aty_ld_lcd(i, par));
1512 pr_cont(" %08X", aty_ld_lcd(i, par));
1525 struct atyfb_par *par = (struct atyfb_par *) info->par;
1531 memcpy(&pll, &par->pll, sizeof(pll));
1537 pixclock = atyfb_get_pixclock(var, par);
1544 err = par->pll_ops->var_to_pll(info, pixclock,
1556 var->pixclock = par->pll_ops->pll_to_var(info, &pll);
1560 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info)
1567 par->crtc.off_pitch =
1579 struct atyfb_par *par = (struct atyfb_par *) info->par;
1582 par->open++;
1584 par->mmaped = 0;
1592 struct atyfb_par *par = dev_id;
1596 spin_lock(&par->int_lock);
1598 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par);
1603 CRTC_VBLANK_INT_AK, par);
1604 par->vblank.count++;
1605 if (par->vblank.pan_display) {
1606 par->vblank.pan_display = 0;
1607 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1609 wake_up_interruptible(&par->vblank.wait);
1613 spin_unlock(&par->int_lock);
1618 static int aty_enable_irq(struct atyfb_par *par, int reenable)
1622 if (!test_and_set_bit(0, &par->irq_flags)) {
1623 if (request_irq(par->irq, aty_irq, IRQF_SHARED, "atyfb", par)) {
1624 clear_bit(0, &par->irq_flags);
1627 spin_lock_irq(&par->int_lock);
1628 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1630 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_AK, par);
1632 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par);
1633 spin_unlock_irq(&par->int_lock);
1635 spin_lock_irq(&par->int_lock);
1636 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1642 CRTC_VBLANK_INT_EN, par);
1644 spin_unlock_irq(&par->int_lock);
1650 static int aty_disable_irq(struct atyfb_par *par)
1654 if (test_and_clear_bit(0, &par->irq_flags)) {
1655 if (par->vblank.pan_display) {
1656 par->vblank.pan_display = 0;
1657 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1659 spin_lock_irq(&par->int_lock);
1660 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1662 aty_st_le32(CRTC_INT_CNTL, int_cntl & ~CRTC_VBLANK_INT_EN, par);
1663 spin_unlock_irq(&par->int_lock);
1664 free_irq(par->irq, par);
1672 struct atyfb_par *par = (struct atyfb_par *) info->par;
1680 par->open--;
1682 wait_for_idle(par);
1684 if (par->open)
1688 was_mmaped = par->mmaped;
1690 par->mmaped = 0;
1716 aty_disable_irq(par);
1730 struct atyfb_par *par = (struct atyfb_par *) info->par;
1733 xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8;
1734 yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
1735 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1739 if (xoffset + xres > par->crtc.vxres ||
1740 yoffset + yres > par->crtc.vyres)
1744 if (par->asleep)
1747 set_off_pitch(par, info);
1748 if ((var->activate & FB_ACTIVATE_VBL) && !aty_enable_irq(par, 0)) {
1749 par->vblank.pan_display = 1;
1751 par->vblank.pan_display = 0;
1752 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1758 static int aty_waitforvblank(struct atyfb_par *par, u32 crtc)
1766 vbl = &par->vblank;
1772 ret = aty_enable_irq(par, 0);
1782 aty_enable_irq(par, 1);
1816 struct atyfb_par *par = (struct atyfb_par *) info->par;
1825 fbtyp.fb_width = par->crtc.vxres;
1826 fbtyp.fb_height = par->crtc.vyres;
1843 return aty_waitforvblank(par, crtc);
1850 union aty_pll *pll = &par->pll;
1853 clk.ref_clk_per = par->ref_clk_per;
1875 union aty_pll *pll = &par->pll;
1879 par->ref_clk_per = clk.ref_clk_per;
1898 if (get_user(par->features, (u32 __user *) arg))
1902 if (put_user(par->features, (u32 __user *) arg))
1914 struct atyfb_par *par = (struct atyfb_par *) info->par;
1916 if (par->blitter_may_be_busy)
1917 wait_for_idle(par);
1924 struct atyfb_par *par = (struct atyfb_par *) info->par;
1930 if (!par->mmap_map)
1950 for (i = 0; par->mmap_map[i].size; i++) {
1951 unsigned long start = par->mmap_map[i].voff;
1952 unsigned long end = start + par->mmap_map[i].size;
1960 map_size = par->mmap_map[i].size - (offset - start);
1961 map_offset = par->mmap_map[i].poff + (offset - start);
1971 pgprot_val(vma->vm_page_prot) &= ~(par->mmap_map[i].prot_mask);
1972 pgprot_val(vma->vm_page_prot) |= par->mmap_map[i].prot_flag;
1984 if (!par->mmaped)
1985 par->mmaped = 1;
1997 static int aty_power_mgmt(int sleep, struct atyfb_par *par)
2002 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2004 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2005 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2011 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2012 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2016 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2017 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2020 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2022 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2030 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2031 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2035 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2036 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2039 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2041 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2057 struct atyfb_par *par = (struct atyfb_par *) info->par;
2067 wait_for_idle(par);
2068 aty_reset_engine(par);
2073 par->asleep = 1;
2074 par->lock_blank = 1;
2084 if (machine_is(powermac) && aty_power_mgmt(1, par)) {
2085 par->asleep = 0;
2086 par->lock_blank = 0;
2118 struct atyfb_par *par = info->par;
2120 aty_st_le32(MEM_CNTL, par->mem_cntl, par);
2122 if (par->pll_ops->resume_pll)
2123 par->pll_ops->resume_pll(info, &par->pll);
2125 if (par->aux_start)
2127 aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2134 struct atyfb_par *par = (struct atyfb_par *) info->par;
2150 aty_power_mgmt(0, par);
2155 par->asleep = 0;
2164 par->lock_blank = 0;
2191 static int aty_bl_get_level_brightness(struct atyfb_par *par, int level)
2193 struct fb_info *info = pci_get_drvdata(par->pdev);
2210 struct atyfb_par *par = bl_get_data(bd);
2211 unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par);
2223 reg |= (aty_bl_get_level_brightness(par, level) << BIAS_MOD_LEVEL_SHIFT);
2226 reg |= (aty_bl_get_level_brightness(par, 0) << BIAS_MOD_LEVEL_SHIFT);
2228 aty_st_lcd(LCD_MISC_CNTL, reg, par);
2237 static void aty_bl_init(struct atyfb_par *par)
2240 struct fb_info *info = pci_get_drvdata(par->pdev);
2254 bd = backlight_device_register(name, info->dev, par, &aty_bl_data,
2289 static void aty_calc_mem_refresh(struct atyfb_par *par, int xclk)
2313 par->mem_refresh_rate = i;
2323 static int atyfb_get_timings_from_lcd(struct atyfb_par *par,
2328 if (par->lcd_table != 0 && (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2330 var->xres = var->xres_virtual = par->lcd_hdisp;
2331 var->right_margin = par->lcd_right_margin;
2332 var->left_margin = par->lcd_hblank_len -
2333 (par->lcd_right_margin + par->lcd_hsync_dly +
2334 par->lcd_hsync_len);
2335 var->hsync_len = par->lcd_hsync_len + par->lcd_hsync_dly;
2336 var->yres = var->yres_virtual = par->lcd_vdisp;
2337 var->lower_margin = par->lcd_lower_margin;
2338 var->upper_margin = par->lcd_vblank_len -
2339 (par->lcd_lower_margin + par->lcd_vsync_len);
2340 var->vsync_len = par->lcd_vsync_len;
2341 var->pixclock = par->lcd_pixclock;
2351 struct atyfb_par *par = (struct atyfb_par *) info->par;
2357 init_waitqueue_head(&par->vblank.wait);
2358 spin_lock_init(&par->int_lock);
2364 stat0 = aty_ld_le32(CNFG_STAT0, par);
2365 par->bus_type = (stat0 >> 0) & 0x07;
2366 par->ram_type = (stat0 >> 3) & 0x07;
2367 ramname = aty_gx_ram[par->ram_type];
2369 dac_type = (aty_ld_le32(DAC_CNTL, par) >> 16) & 0x07;
2376 dac_subtype = (aty_ld_8(SCRATCH_REG1 + 1, par) & 0xF0) | dac_type;
2384 par->dac_ops = &aty_dac_ibm514;
2389 par->dac_ops = &aty_dac_ati68860b;
2393 par->dac_ops = &aty_dac_att21c498;
2398 par->dac_ops = &aty_dac_unsupported;
2404 par->pll_ops = &aty_pll_ati18818_1;
2408 par->pll_ops = &aty_pll_ibm514;
2413 par->pll_ops = &aty_pll_unsupported;
2420 par->dac_ops = &aty_dac_ct;
2421 par->pll_ops = &aty_pll_ct;
2422 par->bus_type = PCI;
2423 par->ram_type = (aty_ld_le32(CNFG_STAT0, par) & 0x07);
2425 ramname = aty_xl_ram[par->ram_type];
2427 ramname = aty_ct_ram[par->ram_type];
2429 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
2430 par->pll_limits.mclk = 63;
2432 if (M64_HAS(MOBIL_BUS) && par->ram_type == SDRAM32)
2433 par->pll_limits.xclk = (par->pll_limits.xclk + 1) >> 1;
2442 par->pll_limits.mclk = 70;
2443 par->pll_limits.xclk = 53;
2449 par->pll_limits.pll_max = pll;
2451 par->pll_limits.mclk = mclk;
2453 par->pll_limits.xclk = xclk;
2455 aty_calc_mem_refresh(par, par->pll_limits.xclk);
2456 par->pll_per = 1000000/par->pll_limits.pll_max;
2457 par->mclk_per = 1000000/par->pll_limits.mclk;
2458 par->xclk_per = 1000000/par->pll_limits.xclk;
2460 par->ref_clk_per = 1000000000000ULL / 14318180;
2465 u8 pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
2469 diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max;
2470 diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max;
2476 par->ref_clk_per = 1000000000000ULL / 29498928;
2484 aty_get_crtc(par, &par->saved_crtc);
2485 if (par->pll_ops->get_pll)
2486 par->pll_ops->get_pll(info, &par->saved_pll);
2488 par->mem_cntl = aty_ld_le32(MEM_CNTL, par);
2492 switch (par->mem_cntl & 0xF) {
2514 switch (par->mem_cntl & MEM_SIZE_ALIAS) {
2538 if (aty_ld_le32(CNFG_STAT1, par) & 0x40000000)
2544 par->mem_cntl &= ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
2546 par->mem_cntl |= MEM_SIZE_512K;
2548 par->mem_cntl |= MEM_SIZE_1M;
2550 par->mem_cntl |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
2552 par->mem_cntl |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
2554 par->mem_cntl |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
2556 par->mem_cntl |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
2557 aty_st_le32(MEM_CNTL, par->mem_cntl, par);
2583 par->pll_limits.pll_max, par->pll_limits.mclk,
2584 par->pll_limits.xclk);
2596 aty_ld_le32(BUS_CNTL, par),
2597 aty_ld_le32(DAC_CNTL, par),
2598 aty_ld_le32(MEM_CNTL, par),
2599 aty_ld_le32(EXT_MEM_CNTL, par),
2600 aty_ld_le32(CRTC_GEN_CNTL, par),
2601 aty_ld_le32(DSP_CONFIG, par),
2602 aty_ld_le32(DSP_ON_OFF, par),
2603 aty_ld_le32(CLOCK_CNTL, par));
2605 pr_cont(" %02x", aty_ld_pll_ct(i, par));
2609 if (par->pll_ops->init_pll)
2610 par->pll_ops->init_pll(info, &par->pll);
2611 if (par->pll_ops->resume_pll)
2612 par->pll_ops->resume_pll(info, &par->pll);
2621 if (par->aux_start)
2622 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) |
2623 BUS_APER_REG_DIS, par);
2630 par->wc_cookie = arch_phys_wc_add(par->res_start,
2631 par->res_size);
2634 info->pseudo_palette = par->pseudo_palette;
2648 aty_st_lcd(POWER_MANAGEMENT, aty_ld_lcd(POWER_MANAGEMENT, par) |
2649 USE_F32KHZ | TRISTATE_MEM_EN, par);
2654 aty_bl_init(par);
2681 sense = read_aty_sense(par);
2698 if (!atyfb_get_timings_from_lcd(par, &var))
2752 info->node, info->fix.id, par->bus_type == ISA ? "ISA" : "PCI");
2757 aty_set_crtc(par, &par->saved_crtc);
2758 par->pll_ops->set_pll(info, &par->saved_pll);
2759 arch_phys_wc_del(par->wc_cookie);
2801 struct atyfb_par *par = (struct atyfb_par *) info->par;
2804 if (par->lock_blank || par->asleep)
2808 if (par->lcd_table && blank > FB_BLANK_NORMAL &&
2809 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2810 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2812 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2816 gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2834 aty_st_le32(CRTC_GEN_CNTL, gen_cntl, par);
2837 if (par->lcd_table && blank <= FB_BLANK_NORMAL &&
2838 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2839 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2841 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2849 const struct atyfb_par *par)
2851 aty_st_8(DAC_W_INDEX, regno, par);
2852 aty_st_8(DAC_DATA, red, par);
2853 aty_st_8(DAC_DATA, green, par);
2854 aty_st_8(DAC_DATA, blue, par);
2867 struct atyfb_par *par = (struct atyfb_par *) info->par;
2875 if (par->asleep)
2887 par->palette[regno].red = red;
2888 par->palette[regno].green = green;
2889 par->palette[regno].blue = blue;
2909 i = aty_ld_8(DAC_CNTL, par) & 0xfc;
2912 aty_st_8(DAC_CNTL, i, par);
2913 aty_st_8(DAC_MASK, 0xff, par);
2919 par->palette[regno << 1].green,
2920 blue, par);
2921 red = par->palette[regno >> 1].red;
2922 blue = par->palette[regno >> 1].blue;
2927 aty_st_pal(regno + i, red, green, blue, par);
2930 aty_st_pal(regno, red, green, blue, par);
2942 struct atyfb_par *par = info->par;
2950 par->ati_regbase = (void *)addr + 0x7ffc00UL;
2967 par->mmap_map = kcalloc(j, sizeof(*par->mmap_map), GFP_ATOMIC);
2968 if (!par->mmap_map) {
2997 par->mmap_map[j].voff = (pbase + 0x10000000) & PAGE_MASK;
2998 par->mmap_map[j].poff = base & PAGE_MASK;
2999 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
3000 par->mmap_map[j].prot_mask = _PAGE_CACHE;
3001 par->mmap_map[j].prot_flag = _PAGE_E;
3010 par->mmap_map[j].voff = (pbase + 0x800000) & PAGE_MASK;
3011 par->mmap_map[j].poff = (base + 0x800000) & PAGE_MASK;
3012 par->mmap_map[j].size = 0x800000;
3013 par->mmap_map[j].prot_mask = _PAGE_CACHE;
3014 par->mmap_map[j].prot_flag = _PAGE_E | _PAGE_IE;
3019 par->mmap_map[j].voff = pbase & PAGE_MASK;
3020 par->mmap_map[j].poff = base & PAGE_MASK;
3021 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
3022 par->mmap_map[j].prot_mask = _PAGE_CACHE;
3023 par->mmap_map[j].prot_flag = _PAGE_E;
3027 ret = correct_chipset(par);
3035 mem = aty_ld_le32(MEM_CNTL, par);
3036 chip_id = aty_ld_le32(CNFG_CHIP_ID, par);
3054 if ((aty_ld_le32(CNFG_STAT0, par) & 7) >= SDRAM)
3058 aty_st_le32(MEM_CNTL, mem, par);
3074 crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
3075 crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
3076 crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
3077 crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
3078 crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
3087 clock_cntl = aty_ld_8(CLOCK_CNTL, par);
3090 pll_regs[i] = aty_ld_pll_ct(i, par);
3139 static void aty_init_lcd(struct atyfb_par *par, u32 bios_base)
3163 par->lcd_table = 0;
3165 par->lcd_table = bios_base + lcd_ofs;
3168 if (par->lcd_table != 0) {
3187 id = *(u8 *)par->lcd_table;
3188 strncpy(model, (char *)par->lcd_table+1, 24);
3191 width = par->lcd_width = *(u16 *)(par->lcd_table+25);
3192 height = par->lcd_height = *(u16 *)(par->lcd_table+27);
3193 panel_type = *(u16 *)(par->lcd_table+29);
3222 format = *(u32 *)(par->lcd_table+57);
3266 refresh_rates = *(u16 *)(par->lcd_table+62);
3283 default_refresh_rate = (*(u8 *)(par->lcd_table+61) & 0xf0) >> 4;
3286 par->lcd_refreshrate = lcd_refresh_rates[default_refresh_rate];
3299 lcdmodeptr = (u16 *)(par->lcd_table + 64);
3309 par->lcd_pixclock = 100000000 / *((u16 *)(modeptr+9));
3310 par->lcd_htotal = *((u16 *)(modeptr+17)) & 511;
3311 par->lcd_hdisp = *((u16 *)(modeptr+19)) & 511;
3313 par->lcd_hsync_dly = (*((u16 *)(modeptr+21)) >> 9) & 7;
3314 par->lcd_hsync_len = *((u8 *)(modeptr+23)) & 63;
3316 par->lcd_vtotal = *((u16 *)(modeptr+24)) & 2047;
3317 par->lcd_vdisp = *((u16 *)(modeptr+26)) & 2047;
3319 par->lcd_vsync_len = (*((u16 *)(modeptr+28)) >> 11) & 31;
3321 par->lcd_htotal = (par->lcd_htotal + 1) * 8;
3322 par->lcd_hdisp = (par->lcd_hdisp + 1) * 8;
3324 par->lcd_hsync_len = par->lcd_hsync_len * 8;
3326 par->lcd_vtotal++;
3327 par->lcd_vdisp++;
3330 par->lcd_right_margin = lcd_hsync_start - par->lcd_hdisp;
3331 par->lcd_lower_margin = lcd_vsync_start - par->lcd_vdisp;
3332 par->lcd_hblank_len = par->lcd_htotal - par->lcd_hdisp;
3333 par->lcd_vblank_len = par->lcd_vtotal - par->lcd_vdisp;
3344 1000000 / par->lcd_pixclock, 1000000 % par->lcd_pixclock,
3345 par->lcd_hdisp,
3346 par->lcd_hdisp + par->lcd_right_margin,
3347 par->lcd_hdisp + par->lcd_right_margin
3348 + par->lcd_hsync_dly + par->lcd_hsync_len,
3349 par->lcd_htotal,
3350 par->lcd_vdisp,
3351 par->lcd_vdisp + par->lcd_lower_margin,
3352 par->lcd_vdisp + par->lcd_lower_margin + par->lcd_vsync_len,
3353 par->lcd_vtotal);
3355 par->lcd_pixclock,
3356 par->lcd_hblank_len - (par->lcd_right_margin +
3357 par->lcd_hsync_dly + par->lcd_hsync_len),
3358 par->lcd_hdisp,
3359 par->lcd_right_margin,
3360 par->lcd_hsync_len,
3361 par->lcd_vblank_len - (par->lcd_lower_margin + par->lcd_vsync_len),
3362 par->lcd_vdisp,
3363 par->lcd_lower_margin,
3364 par->lcd_vsync_len);
3370 static int init_from_bios(struct atyfb_par *par)
3375 rom_addr = 0xc0000 + ((aty_ld_le32(SCRATCH_REG1, par) & 0x7f) << 11);
3401 par->pll_limits.pll_min = pll_block.PCLK_min_freq/100;
3402 par->pll_limits.pll_max = pll_block.PCLK_max_freq/100;
3403 par->pll_limits.ref_clk = pll_block.ref_freq/100;
3404 par->pll_limits.ref_div = pll_block.ref_divider;
3405 par->pll_limits.sclk = pll_block.SCLK_freq/100;
3406 par->pll_limits.mclk = pll_block.MCLK_max_freq/100;
3407 par->pll_limits.mclk_pm = pll_block.MCLK_pwd/100;
3408 par->pll_limits.xclk = pll_block.XCLK_max_freq/100;
3410 aty_init_lcd(par, bios_base);
3426 struct atyfb_par *par = info->par;
3436 par->aux_start = rrp->start;
3437 par->aux_size = resource_size(rrp);
3448 par->ati_regbase = ioremap_uc(info->fix.mmio_start, 0x1000);
3450 par->ati_regbase = ioremap(info->fix.mmio_start, 0x1000);
3452 if (par->ati_regbase == NULL)
3455 info->fix.mmio_start += par->aux_start ? 0x400 : 0xc00;
3456 par->ati_regbase += par->aux_start ? 0x400 : 0xc00;
3497 ret = correct_chipset(par);
3501 ret = init_from_bios(par);
3505 if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN))
3506 par->clk_wr_offset = (inb(R_GENMO) & 0x0CU) >> 2;
3508 par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
3511 par->clk_wr_offset = 3;
3516 iounmap(par->ati_regbase);
3517 par->ati_regbase = NULL;
3533 struct atyfb_par *par;
3561 par = info->par;
3562 par->bus_type = PCI;
3565 par->pci_id = pdev->device;
3566 par->res_start = res_start;
3567 par->res_size = res_size;
3568 par->irq = pdev->irq;
3569 par->pdev = pdev;
3591 par->mmap_map[0].voff = 0x8000000000000000UL;
3592 par->mmap_map[0].poff = (unsigned long) info->screen_base & PAGE_MASK;
3593 par->mmap_map[0].size = info->fix.smem_len;
3594 par->mmap_map[0].prot_mask = _PAGE_CACHE;
3595 par->mmap_map[0].prot_flag = _PAGE_E;
3596 par->mmap_map[1].voff = par->mmap_map[0].voff + info->fix.smem_len;
3597 par->mmap_map[1].poff = (long)par->ati_regbase & PAGE_MASK;
3598 par->mmap_map[1].size = PAGE_SIZE;
3599 par->mmap_map[1].prot_mask = _PAGE_CACHE;
3600 par->mmap_map[1].prot_flag = _PAGE_E;
3612 kfree(par->mmap_map);
3614 if (par->ati_regbase)
3615 iounmap(par->ati_regbase);
3620 if (par->aux_start)
3621 release_mem_region(par->aux_start, par->aux_size);
3623 release_mem_region(par->res_start, par->res_size);
3635 struct atyfb_par *par;
3653 par = info->par;
3657 par->irq = (unsigned int) -1; /* something invalid */
3666 par->ati_regbase = ioremap(phys_guiregbase[m64_num], 0x10000) +
3668 info->fix.mmio_start = (unsigned long)par->ati_regbase; /* Fake! */
3670 aty_st_le32(CLOCK_CNTL, 0x12345678, par);
3671 clock_r = aty_ld_le32(CLOCK_CNTL, par);
3675 par->clk_wr_offset = 3; /* */
3678 par->clk_wr_offset = 2; /* Medusa ST-IO ISA Adapter etc. */
3681 par->clk_wr_offset = 1; /* */
3684 par->clk_wr_offset = 0; /* Panther 1 ISA Adapter (Gerald) */
3689 switch (aty_ld_le32(CNFG_CHIP_ID, par) & CFG_CHIP_TYPE) {
3691 par->pci_id = PCI_CHIP_MACH64GX;
3694 par->pci_id = PCI_CHIP_MACH64CX;
3700 if (correct_chipset(par) || aty_init(info)) {
3702 iounmap(par->ati_regbase);
3718 struct atyfb_par *par = (struct atyfb_par *) info->par;
3721 aty_set_crtc(par, &par->saved_crtc);
3722 par->pll_ops->set_pll(info, &par->saved_pll);
3730 arch_phys_wc_del(par->wc_cookie);
3733 if (par->ati_regbase)
3734 iounmap(par->ati_regbase);
3743 kfree(par->mmap_map);
3745 if (par->aux_start)
3746 release_mem_region(par->aux_start, par->aux_size);
3748 if (par->res_start)
3749 release_mem_region(par->res_start, par->res_size);
3909 struct atyfb_par *par;
3921 par = reboot_info->par;
3928 aty_set_crtc(par, &par->saved_crtc);
3929 par->pll_ops->set_pll(reboot_info, &par->saved_pll);