Lines Matching refs:vclk
426 u32 vclk;
1365 u32 vclk; /* in .01 MHz */
1369 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */
1372 if (vclk > c.ppll_max)
1373 vclk = c.ppll_max;
1374 if (vclk * 12 < c.ppll_min)
1375 vclk = c.ppll_min/12;
1379 output_freq = post_dividers[i] * vclk;
1394 pll->vclk = vclk;
1398 pll->feedback_divider, vclk, output_freq,
1408 var->pixclock = 100000000 / pll->vclk;
1438 d = pll->vclk * bpp;