Lines Matching defs:par
480 const struct aty128fb_par *par);
482 struct aty128fb_par *par);
483 static void aty128_timings(struct aty128fb_par *par);
484 static void aty128_init_engine(struct aty128fb_par *par);
485 static void aty128_reset_engine(const struct aty128fb_par *par);
486 static void aty128_flush_pixel_cache(const struct aty128fb_par *par);
487 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par);
488 static void wait_for_fifo(u16 entries, struct aty128fb_par *par);
489 static void wait_for_idle(struct aty128fb_par *par);
525 const struct aty128fb_par *par)
527 return readl (par->regbase + regindex);
531 const struct aty128fb_par *par)
533 writel (val, par->regbase + regindex);
537 const struct aty128fb_par *par)
539 return readb (par->regbase + regindex);
543 const struct aty128fb_par *par)
545 writeb (val, par->regbase + regindex);
548 #define aty_ld_le32(regindex) _aty_ld_le32(regindex, par)
549 #define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, par)
550 #define aty_ld_8(regindex) _aty_ld_8(regindex, par)
551 #define aty_st_8(regindex, val) _aty_st_8(regindex, val, par)
557 #define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, par)
558 #define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, par)
562 const struct aty128fb_par *par)
570 const struct aty128fb_par *par)
578 static int aty_pll_readupdate(const struct aty128fb_par *par)
584 static void aty_pll_wait_readupdate(const struct aty128fb_par *par)
590 if (aty_pll_readupdate(par)) {
601 static void aty_pll_writeupdate(const struct aty128fb_par *par)
603 aty_pll_wait_readupdate(par);
611 static int register_test(const struct aty128fb_par *par)
634 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par)
640 par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff;
641 if (par->fifo_slots >= entries)
644 aty128_reset_engine(par);
649 static void wait_for_idle(struct aty128fb_par *par)
653 do_wait_for_fifo(64, par);
658 aty128_flush_pixel_cache(par);
659 par->blitter_may_be_busy = 0;
663 aty128_reset_engine(par);
668 static void wait_for_fifo(u16 entries, struct aty128fb_par *par)
670 if (par->fifo_slots < entries)
671 do_wait_for_fifo(64, par);
672 par->fifo_slots -= entries;
676 static void aty128_flush_pixel_cache(const struct aty128fb_par *par)
692 static void aty128_reset_engine(const struct aty128fb_par *par)
696 aty128_flush_pixel_cache(par);
720 static void aty128_init_engine(struct aty128fb_par *par)
724 wait_for_idle(par);
727 wait_for_fifo(1, par);
730 aty128_reset_engine(par);
732 pitch_value = par->crtc.pitch;
733 if (par->crtc.bpp == 24) {
737 wait_for_fifo(4, par);
754 (depth_to_dst(par->crtc.depth) << 8) |
765 wait_for_fifo(8, par);
783 wait_for_idle(par);
810 static void __iomem *aty128_map_ROM(const struct aty128fb_par *par,
897 static void aty128_get_pllinfo(struct aty128fb_par *par,
906 par->constants.ppll_max = BIOS_IN32(bios_pll + 0x16);
907 par->constants.ppll_min = BIOS_IN32(bios_pll + 0x12);
908 par->constants.xclk = BIOS_IN16(bios_pll + 0x08);
909 par->constants.ref_divider = BIOS_IN16(bios_pll + 0x10);
910 par->constants.ref_clk = BIOS_IN16(bios_pll + 0x0e);
913 par->constants.ppll_max, par->constants.ppll_min,
914 par->constants.xclk, par->constants.ref_divider,
915 par->constants.ref_clk);
920 static void __iomem *aty128_find_mem_vbios(struct aty128fb_par *par)
945 static void aty128_timings(struct aty128fb_par *par)
958 if (!par->constants.ref_clk)
959 par->constants.ref_clk = 2950;
967 par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk),
970 par->constants.ref_divider =
974 if (!par->constants.ref_divider) {
975 par->constants.ref_divider = 0x3b;
978 aty_pll_writeupdate(par);
980 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider);
981 aty_pll_writeupdate(par);
984 if (!par->constants.ppll_min)
985 par->constants.ppll_min = 12500;
986 if (!par->constants.ppll_max)
987 par->constants.ppll_max = 25000; /* 23000 on some cards? */
988 if (!par->constants.xclk)
989 par->constants.xclk = 0x1d4d; /* same as mclk */
991 par->constants.fifo_width = 128;
992 par->constants.fifo_depth = 32;
996 par->mem = &sdr_128;
999 par->mem = &sdr_sgram;
1002 par->mem = &ddr_sgram;
1005 par->mem = &sdr_sgram;
1017 const struct aty128fb_par *par)
1034 const struct aty128fb_par *par)
1092 if ((u32)(vxres * vyres * bytpp) > par->vram_size) {
1279 static void aty128_set_crt_enable(struct aty128fb_par *par, int on)
1291 static void aty128_set_lcd_enable(struct aty128fb_par *par, int on)
1295 struct fb_info *info = pci_get_drvdata(par->pdev);
1320 const struct aty128fb_par *par)
1335 aty_pll_wait_readupdate(par);
1336 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff);
1337 aty_pll_writeupdate(par);
1346 aty_pll_wait_readupdate(par);
1348 aty_pll_writeupdate(par);
1350 aty_pll_wait_readupdate(par);
1352 aty_pll_writeupdate(par);
1360 const struct aty128fb_par *par)
1362 const struct aty128_constants c = par->constants;
1415 const struct aty128fb_par *par)
1425 const struct aty128fb_par *par)
1427 const struct aty128_meminfo *m = par->mem;
1428 u32 xclk = par->constants.xclk;
1429 u32 fifo_width = par->constants.fifo_width;
1430 u32 fifo_depth = par->constants.fifo_depth;
1484 struct aty128fb_par *par = info->par;
1488 if ((err = aty128_decode_var(&info->var, par)) != 0)
1491 if (par->blitter_may_be_busy)
1492 wait_for_idle(par);
1510 aty128_set_crtc(&par->crtc, par);
1511 aty128_set_pll(&par->pll, par);
1512 aty128_set_fifo(&par->fifo_reg, par);
1517 if (par->crtc.bpp == 32)
1519 else if (par->crtc.bpp == 16)
1526 info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3;
1527 info->fix.visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR
1530 if (par->chip_gen == rage_M3) {
1531 aty128_set_crt_enable(par, par->crt_on);
1532 aty128_set_lcd_enable(par, par->lcd_on);
1534 if (par->accel_flags & FB_ACCELF_TEXT)
1535 aty128_init_engine(par);
1539 (((par->crtc.h_total>>16) & 0xff)+1)*8,
1540 ((par->crtc.v_total>>16) & 0x7ff)+1,
1541 par->crtc.bpp,
1542 par->crtc.vxres*par->crtc.bpp/8);
1553 struct aty128fb_par *par)
1560 if ((err = aty128_var_to_crtc(var, &crtc, par)))
1563 if ((err = aty128_var_to_pll(var->pixclock, &pll, par)))
1566 if ((err = aty128_ddafifo(&fifo_reg, &pll, crtc.depth, par)))
1569 par->crtc = crtc;
1570 par->pll = pll;
1571 par->fifo_reg = fifo_reg;
1572 par->accel_flags = var->accel_flags;
1579 const struct aty128fb_par *par)
1583 if ((err = aty128_crtc_to_var(&par->crtc, var)))
1586 if ((err = aty128_pll_to_var(&par->pll, var)))
1594 var->accel_flags = par->accel_flags;
1603 struct aty128fb_par par;
1606 par = *(struct aty128fb_par *)info->par;
1607 if ((err = aty128_decode_var(var, &par)) != 0)
1609 aty128_encode_var(var, &par);
1620 struct aty128fb_par *par = fb->par;
1625 xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3;
1626 yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1;
1631 if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres)
1634 par->crtc.xoffset = xoffset;
1635 par->crtc.yoffset = yoffset;
1637 offset = ((yoffset * par->crtc.vxres + xoffset) * (par->crtc.bpp >> 3))
1640 if (par->crtc.bpp == 24)
1653 struct aty128fb_par *par)
1655 if (par->chip_gen == rage_M3) {
1666 struct aty128fb_par *par = info->par;
1668 if (par->blitter_may_be_busy)
1669 wait_for_idle(par);
1734 static int aty128_bl_get_level_brightness(struct aty128fb_par *par,
1737 struct fb_info *info = pci_get_drvdata(par->pdev);
1763 struct aty128fb_par *par = bl_get_data(bd);
1769 !par->lcd_on)
1786 reg |= (aty128_bl_get_level_brightness(par, level) <<
1798 reg |= (aty128_bl_get_level_brightness(par, 0) <<
1828 static void aty128_bl_init(struct aty128fb_par *par)
1831 struct fb_info *info = pci_get_drvdata(par->pdev);
1836 if (par->chip_gen != rage_M3)
1849 bd = backlight_device_register(name, info->dev, par, &aty128_bl_data,
1888 struct aty128fb_par *par = data;
1892 pci_restore_state(par->pdev);
1893 aty128_do_resume(par->pdev);
1901 struct aty128fb_par *par = info->par;
1921 if (par->vram_size % (1024 * 1024) == 0)
1922 printk("%dM %s\n", par->vram_size / (1024*1024), par->mem->name);
1924 printk("%dk %s\n", par->vram_size / 1024, par->mem->name);
1926 par->chip_gen = ent->driver_data;
1932 par->lcd_on = default_lcd_on;
1933 par->crt_on = default_crt_on;
1939 if (par->chip_gen == rage_M3) {
1947 pmac_set_early_video_resume(aty128_early_resume, par);
2013 if (par->chip_gen == rage_M3)
2025 aty128_init_engine(par);
2027 par->pdev = pdev;
2028 par->asleep = 0;
2029 par->lock_blank = 0;
2033 aty128_bl_init(par);
2050 struct aty128fb_par *par;
2084 par = info->par;
2086 info->pseudo_palette = par->pseudo_palette;
2090 par->regbase = pci_ioremap_bar(pdev, 2);
2091 if (!par->regbase)
2096 par->vram_size = aty_ld_le32(CNFG_MEMSIZE) & 0x03FFFFFF;
2099 info->screen_base = ioremap_wc(fb_addr, par->vram_size);
2106 info->fix.smem_len = par->vram_size;
2110 if (!register_test(par)) {
2116 bios = aty128_map_ROM(par, pdev);
2119 bios = aty128_find_mem_vbios(par);
2125 aty128_get_pllinfo(par, bios);
2130 aty128_timings(par);
2137 par->wc_cookie = arch_phys_wc_add(info->fix.smem_start,
2138 par->vram_size);
2144 iounmap(par->regbase);
2159 struct aty128fb_par *par;
2164 par = info->par;
2172 arch_phys_wc_del(par->wc_cookie);
2173 iounmap(par->regbase);
2191 struct aty128fb_par *par = fb->par;
2194 if (par->lock_blank || par->asleep)
2217 if (par->chip_gen == rage_M3) {
2218 aty128_set_crt_enable(par, par->crt_on && !blank);
2219 aty128_set_lcd_enable(par, par->lcd_on && !blank);
2233 struct aty128fb_par *par = info->par;
2236 || (par->crtc.depth == 16 && regno > 63)
2237 || (par->crtc.depth == 15 && regno > 31))
2248 switch (par->crtc.depth) {
2265 if (par->crtc.depth == 16 && regno > 0) {
2273 par->green[regno] = green;
2275 par->red[regno] = red;
2276 par->blue[regno] = blue;
2277 aty128_st_pal(regno * 8, red, par->green[regno*2],
2278 blue, par);
2280 red = par->red[regno/2];
2281 blue = par->blue[regno/2];
2283 } else if (par->crtc.bpp == 16)
2285 aty128_st_pal(regno, red, green, blue, par);
2300 struct aty128fb_par *par = info->par;
2306 if (par->chip_gen != rage_M3)
2311 par->lcd_on = (value & 0x01) != 0;
2312 par->crt_on = (value & 0x02) != 0;
2313 if (!par->crt_on && !par->lcd_on)
2314 par->lcd_on = 1;
2315 aty128_set_crt_enable(par, par->crt_on);
2316 aty128_set_lcd_enable(par, par->lcd_on);
2319 if (par->chip_gen != rage_M3)
2321 value = (par->crt_on << 1) | par->lcd_on;
2327 static void aty128_set_suspend(struct aty128fb_par *par, int suspend)
2331 if (!par->pdev->pm_cap)
2363 struct aty128fb_par *par = info->par;
2389 wait_for_idle(par);
2390 aty128_reset_engine(par);
2391 wait_for_idle(par);
2397 par->asleep = 1;
2398 par->lock_blank = 1;
2414 aty128_set_suspend(par, 1);
2441 struct aty128fb_par *par = info->par;
2452 aty128_set_suspend(par, 0);
2453 par->asleep = 0;
2456 aty128_reset_engine(par);
2457 wait_for_idle(par);
2466 par->lock_blank = 0;