Lines Matching refs:vgabase
151 svga_tilecursor(par->state.vgabase, info, cursor);
467 regval = vga_rseq(par->state.vgabase, 0x1C);
470 vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0));
471 code[1] = vga_r(par->state.vgabase, dac_regs[code[0] & 3]);
476 vga_wseq(par->state.vgabase, 0x1C, regval);
486 regval = vga_rseq(par->state.vgabase, 0x1C);
489 vga_wseq(par->state.vgabase, 0x1C, regval | (code[0] & 4 ? 0x80 : 0));
490 vga_w(par->state.vgabase, dac_regs[code[0] & 3], code[1]);
495 vga_wseq(par->state.vgabase, 0x1C, regval);
511 regval = vga_r(par->state.vgabase, VGA_MIS_R);
512 vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
524 void __iomem *vgabase = par->state.vgabase;
527 par->state.vgabase = vgabase;
654 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80);
657 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
658 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
661 svga_set_default_gfx_regs(par->state.vgabase);
662 svga_set_default_atc_regs(par->state.vgabase);
663 svga_set_default_seq_regs(par->state.vgabase);
664 svga_set_default_crt_regs(par->state.vgabase);
665 svga_wcrt_multi(par->state.vgabase, ark_line_compare_regs, 0xFFFFFFFF);
666 svga_wcrt_multi(par->state.vgabase, ark_start_address_regs, 0);
669 svga_wseq_mask(par->state.vgabase, 0x10, 0x1F, 0x1F); /* enable linear framebuffer and full memory access */
670 svga_wseq_mask(par->state.vgabase, 0x12, 0x03, 0x03); /* 4 MB linear framebuffer size */
672 vga_wseq(par->state.vgabase, 0x13, info->fix.smem_start >> 16);
673 vga_wseq(par->state.vgabase, 0x14, info->fix.smem_start >> 24);
674 vga_wseq(par->state.vgabase, 0x15, 0);
675 vga_wseq(par->state.vgabase, 0x16, 0);
680 vga_wseq(par->state.vgabase, 0x18, regval);
684 svga_wcrt_multi(par->state.vgabase, ark_offset_regs, offset_value);
687 svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08);
690 svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80);
692 svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80);
695 svga_wcrt_mask(par->state.vgabase, 0x44, 0x04, 0x04);
697 svga_wcrt_mask(par->state.vgabase, 0x44, 0x00, 0x04);
707 svga_set_textmode_vga_regs(par->state.vgabase);
709 vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */
710 svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
716 vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40);
718 vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */
719 svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
725 vga_wseq(par->state.vgabase, 0x11, 0x10); /* basic VGA mode */
726 svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
732 vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode */
736 svga_wcrt_mask(par->state.vgabase, 0x46, 0x00, 0x04); /* 8bit pixel path */
740 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
748 vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */
749 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
755 vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */
756 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
762 vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode ??? */
763 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
771 vga_wseq(par->state.vgabase, 0x11, 0x1E); /* 32bpp accel mode */
772 svga_wcrt_mask(par->state.vgabase, 0x46, 0x04, 0x04); /* 16bit pixel path */
787 svga_set_timings(par->state.vgabase, &ark_timing_regs, &(info->var), hmul, hdiv,
795 vga_wcrt(par->state.vgabase, 0x42, (value + 1) / 2);
801 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
802 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
877 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
878 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
882 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
883 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
889 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
890 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
916 svga_wcrt_multi(par->state.vgabase, ark_start_address_regs, offset);
1011 par->state.vgabase = (void __iomem *) (unsigned long) vga_res.start;
1014 regval = vga_rseq(par->state.vgabase, 0x10);