Lines Matching defs:ltv350qv_write_reg
37 static int ltv350qv_write_reg(struct ltv350qv *lcd, u8 reg, u16 val)
73 if (ltv350qv_write_reg(lcd, LTV_PWRCTL1, 0x0000))
78 if (ltv350qv_write_reg(lcd, LTV_PWRCTL1, LTV_VCOM_DISABLE))
80 if (ltv350qv_write_reg(lcd, LTV_PWRCTL2, LTV_VCOML_ENABLE))
84 if (ltv350qv_write_reg(lcd, LTV_PWRCTL1,
92 ret = ltv350qv_write_reg(lcd, LTV_IFCTL,
94 ret |= ltv350qv_write_reg(lcd, LTV_DATACTL,
97 ret |= ltv350qv_write_reg(lcd, LTV_ENTRY_MODE,
103 ret |= ltv350qv_write_reg(lcd, LTV_GATECTL1, LTV_CLW(3));
104 ret |= ltv350qv_write_reg(lcd, LTV_GATECTL2,
106 ret |= ltv350qv_write_reg(lcd, LTV_VBP, 0x000a);
107 ret |= ltv350qv_write_reg(lcd, LTV_HBP, 0x0021);
108 ret |= ltv350qv_write_reg(lcd, LTV_SOTCTL, LTV_SDT(3) | LTV_EQ(0));
109 ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(0), 0x0103);
110 ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(1), 0x0301);
111 ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(2), 0x1f0f);
112 ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(3), 0x1f0f);
113 ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(4), 0x0707);
114 ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(5), 0x0307);
115 ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(6), 0x0707);
116 ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(7), 0x0000);
117 ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(8), 0x0004);
118 ret |= ltv350qv_write_reg(lcd, LTV_GAMMA(9), 0x0000);
126 ret = ltv350qv_write_reg(lcd, LTV_PWRCTL1,
130 ret |= ltv350qv_write_reg(lcd, LTV_GATECTL2,
144 ltv350qv_write_reg(lcd, LTV_PWRCTL1,
147 ltv350qv_write_reg(lcd, LTV_GATECTL2,
152 ltv350qv_write_reg(lcd, LTV_PWRCTL2, 0x0000);
155 ltv350qv_write_reg(lcd, LTV_PWRCTL1, LTV_VCOM_DISABLE);
164 ret = ltv350qv_write_reg(lcd, LTV_PWRCTL1,
168 ret |= ltv350qv_write_reg(lcd, LTV_GATECTL2,
172 ret |= ltv350qv_write_reg(lcd, LTV_PWRCTL2, 0x0000);
178 ret |= ltv350qv_write_reg(lcd, LTV_PWRCTL1, LTV_VCOM_DISABLE);