Lines Matching refs:perm
112 struct perm_bits *perm, int offset, __le32 *val);
114 struct perm_bits *perm, int offset, __le32 val);
175 int count, struct perm_bits *perm,
182 memcpy(&virt, perm->virt + offset, count);
201 int count, struct perm_bits *perm,
206 memcpy(&write, perm->write + offset, count);
211 memcpy(&virt, perm->virt + offset, count);
248 int count, struct perm_bits *perm,
273 int count, struct perm_bits *perm,
286 int count, struct perm_bits *perm,
300 int count, struct perm_bits *perm,
308 int count, struct perm_bits *perm,
338 static void free_perm_bits(struct perm_bits *perm)
340 kfree(perm->virt);
341 kfree(perm->write);
342 perm->virt = NULL;
343 perm->write = NULL;
346 static int alloc_perm_bits(struct perm_bits *perm, int size)
362 perm->virt = kzalloc(size, GFP_KERNEL);
363 perm->write = kzalloc(size, GFP_KERNEL);
364 if (!perm->virt || !perm->write) {
365 free_perm_bits(perm);
369 perm->readfn = vfio_default_config_read;
370 perm->writefn = vfio_default_config_write;
518 int count, struct perm_bits *perm,
524 count = vfio_default_config_read(vdev, pos, count, perm, offset, val);
556 int count, struct perm_bits *perm,
605 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
648 static int __init init_pci_cap_basic_perm(struct perm_bits *perm)
650 if (alloc_perm_bits(perm, PCI_STD_HEADER_SIZEOF))
653 perm->readfn = vfio_basic_config_read;
654 perm->writefn = vfio_basic_config_write;
657 p_setw(perm, PCI_VENDOR_ID, (u16)ALL_VIRT, NO_WRITE);
658 p_setw(perm, PCI_DEVICE_ID, (u16)ALL_VIRT, NO_WRITE);
664 p_setw(perm, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE, (u16)ALL_WRITE);
667 p_setw(perm, PCI_STATUS, PCI_STATUS_CAP_LIST, NO_WRITE);
670 p_setb(perm, PCI_CACHE_LINE_SIZE, NO_VIRT, (u8)ALL_WRITE);
671 p_setb(perm, PCI_LATENCY_TIMER, NO_VIRT, (u8)ALL_WRITE);
672 p_setb(perm, PCI_BIST, NO_VIRT, (u8)ALL_WRITE);
675 p_setd(perm, PCI_BASE_ADDRESS_0, ALL_VIRT, ALL_WRITE);
676 p_setd(perm, PCI_BASE_ADDRESS_1, ALL_VIRT, ALL_WRITE);
677 p_setd(perm, PCI_BASE_ADDRESS_2, ALL_VIRT, ALL_WRITE);
678 p_setd(perm, PCI_BASE_ADDRESS_3, ALL_VIRT, ALL_WRITE);
679 p_setd(perm, PCI_BASE_ADDRESS_4, ALL_VIRT, ALL_WRITE);
680 p_setd(perm, PCI_BASE_ADDRESS_5, ALL_VIRT, ALL_WRITE);
681 p_setd(perm, PCI_ROM_ADDRESS, ALL_VIRT, ALL_WRITE);
684 p_setb(perm, PCI_CAPABILITY_LIST, (u8)ALL_VIRT, NO_WRITE);
687 p_setb(perm, PCI_INTERRUPT_LINE, (u8)ALL_VIRT, (u8)ALL_WRITE);
690 p_setb(perm, PCI_INTERRUPT_PIN, (u8)ALL_VIRT, (u8)NO_WRITE);
696 int count, struct perm_bits *perm,
699 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
728 static int __init init_pci_cap_pm_perm(struct perm_bits *perm)
730 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_PM]))
733 perm->writefn = vfio_pm_config_write;
739 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
746 p_setd(perm, PCI_PM_CTRL, NO_VIRT, ~PCI_PM_CTRL_STATE_MASK);
751 int count, struct perm_bits *perm,
765 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
795 static int __init init_pci_cap_vpd_perm(struct perm_bits *perm)
797 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_VPD]))
800 perm->writefn = vfio_vpd_config_write;
806 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
812 p_setw(perm, PCI_VPD_ADDR, (u16)ALL_VIRT, (u16)ALL_WRITE);
813 p_setd(perm, PCI_VPD_DATA, ALL_VIRT, ALL_WRITE);
819 static int __init init_pci_cap_pcix_perm(struct perm_bits *perm)
822 if (alloc_perm_bits(perm, PCI_CAP_PCIX_SIZEOF_V2))
825 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
827 p_setw(perm, PCI_X_CMD, NO_VIRT, (u16)ALL_WRITE);
828 p_setd(perm, PCI_X_ECC_CSR, NO_VIRT, ALL_WRITE);
833 int count, struct perm_bits *perm,
840 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
892 static int __init init_pci_cap_exp_perm(struct perm_bits *perm)
895 if (alloc_perm_bits(perm, PCI_CAP_EXP_ENDPOINT_SIZEOF_V2))
898 perm->writefn = vfio_exp_config_write;
900 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
909 p_setw(perm, PCI_EXP_DEVCTL,
912 p_setw(perm, PCI_EXP_DEVCTL2, NO_VIRT, ~PCI_EXP_DEVCTL2_ARI);
917 int count, struct perm_bits *perm,
922 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
953 static int __init init_pci_cap_af_perm(struct perm_bits *perm)
955 if (alloc_perm_bits(perm, pci_cap_length[PCI_CAP_ID_AF]))
958 perm->writefn = vfio_af_config_write;
960 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
961 p_setb(perm, PCI_AF_CTRL, PCI_AF_CTRL_FLR, PCI_AF_CTRL_FLR);
966 static int __init init_pci_ext_cap_err_perm(struct perm_bits *perm)
970 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_ERR]))
978 p_setd(perm, 0, ALL_VIRT, NO_WRITE);
998 p_setd(perm, PCI_ERR_UNCOR_STATUS, NO_VIRT, mask);
999 p_setd(perm, PCI_ERR_UNCOR_MASK, NO_VIRT, mask);
1000 p_setd(perm, PCI_ERR_UNCOR_SEVER, NO_VIRT, mask);
1010 p_setd(perm, PCI_ERR_COR_STATUS, NO_VIRT, mask);
1011 p_setd(perm, PCI_ERR_COR_MASK, NO_VIRT, mask);
1015 p_setd(perm, PCI_ERR_CAP, NO_VIRT, mask);
1020 static int __init init_pci_ext_cap_pwr_perm(struct perm_bits *perm)
1022 if (alloc_perm_bits(perm, pci_ext_cap_length[PCI_EXT_CAP_ID_PWR]))
1025 p_setd(perm, 0, ALL_VIRT, NO_WRITE);
1028 p_setb(perm, PCI_PWR_DATA, NO_VIRT, (u8)ALL_WRITE);
1093 int count, struct perm_bits *perm,
1109 return vfio_default_config_read(vdev, pos, count, perm, offset, val);
1113 int count, struct perm_bits *perm,
1116 count = vfio_default_config_write(vdev, pos, count, perm, offset, val);
1158 static int init_pci_cap_msi_perm(struct perm_bits *perm, int len, u16 flags)
1160 if (alloc_perm_bits(perm, len))
1163 perm->readfn = vfio_msi_config_read;
1164 perm->writefn = vfio_msi_config_write;
1166 p_setb(perm, PCI_CAP_LIST_NEXT, (u8)ALL_VIRT, NO_WRITE);
1172 p_setb(perm, PCI_MSI_FLAGS, (u8)ALL_VIRT, (u8)ALL_WRITE);
1173 p_setd(perm, PCI_MSI_ADDRESS_LO, ALL_VIRT, ALL_WRITE);
1175 p_setd(perm, PCI_MSI_ADDRESS_HI, ALL_VIRT, ALL_WRITE);
1176 p_setw(perm, PCI_MSI_DATA_64, (u16)ALL_VIRT, (u16)ALL_WRITE);
1178 p_setd(perm, PCI_MSI_MASK_64, NO_VIRT, ALL_WRITE);
1179 p_setd(perm, PCI_MSI_PENDING_64, NO_VIRT, ALL_WRITE);
1182 p_setw(perm, PCI_MSI_DATA_32, (u16)ALL_VIRT, (u16)ALL_WRITE);
1184 p_setd(perm, PCI_MSI_MASK_32, NO_VIRT, ALL_WRITE);
1185 p_setd(perm, PCI_MSI_PENDING_32, NO_VIRT, ALL_WRITE);
1809 struct perm_bits *perm;
1836 perm = &unassigned_perms;
1839 perm = &virt_perms;
1845 perm = &ecap_perms[cap_id];
1850 perm = &cap_perms[cap_id];
1853 perm = vdev->msi_perm;
1866 if (!perm->writefn)
1872 ret = perm->writefn(vdev, *ppos, count, perm, offset, val);
1874 if (perm->readfn) {
1875 ret = perm->readfn(vdev, *ppos, count,
1876 perm, offset, &val);