Lines Matching refs:fact
157 #define CH341_CLK_DIV(ps, fact) (1 << (12 - 3 * (ps) - (fact)))
174 * baudrate = 48000000 / (2^(12 - 3 * ps - fact) * div), where
177 * 0 <= fact <= 1,
178 * 2 <= div <= 256 if fact = 0, or
179 * 9 <= div <= 256 if fact = 1
183 unsigned int fact, div, clk_div;
194 * Start with highest possible base clock (fact = 1) that will give a
197 fact = 1;
207 clk_div = CH341_CLK_DIV(ps, fact);
214 /* Halve base clock (fact = 0) if required. */
218 fact = 0;
233 * Prefer lower base clock (fact = 0) if even divisor.
237 if (fact == 1 && div % 2 == 0) {
239 fact = 0;
242 return (0x100 - div) << 8 | fact << 2 | ps;