Lines Matching refs:base
205 void __iomem *base = phy->regs;
209 val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC);
212 writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC);
214 val = readl_relaxed(base + TEGRA_USB_PORTSC1);
218 writel_relaxed(val, base + TEGRA_USB_PORTSC1);
224 void __iomem *base = phy->regs;
228 val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC);
233 writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC);
235 val = readl_relaxed(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS;
240 writel_relaxed(val, base + TEGRA_USB_PORTSC1);
311 void __iomem *base = phy->pad_regs;
322 val = readl_relaxed(base + UTMIP_BIAS_CFG0);
334 writel_relaxed(val, base + UTMIP_BIAS_CFG0);
346 void __iomem *base = phy->pad_regs;
363 val = readl_relaxed(base + UTMIP_BIAS_CFG0);
365 writel_relaxed(val, base + UTMIP_BIAS_CFG0);
385 void __iomem *base = phy->regs;
393 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) == 0)
397 val = readl_relaxed(base + USB_SUSP_CTRL);
399 writel_relaxed(val, base + USB_SUSP_CTRL);
403 val = readl_relaxed(base + USB_SUSP_CTRL);
405 writel_relaxed(val, base + USB_SUSP_CTRL);
410 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0))
417 void __iomem *base = phy->regs;
425 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
430 val = readl_relaxed(base + USB_SUSP_CTRL);
432 writel_relaxed(val, base + USB_SUSP_CTRL);
436 val = readl_relaxed(base + USB_SUSP_CTRL);
438 writel_relaxed(val, base + USB_SUSP_CTRL);
443 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
452 void __iomem *base = phy->regs;
456 val = readl_relaxed(base + USB_SUSP_CTRL);
458 writel_relaxed(val, base + USB_SUSP_CTRL);
461 val = readl_relaxed(base + USB1_LEGACY_CTRL);
463 writel_relaxed(val, base + USB1_LEGACY_CTRL);
466 val = readl_relaxed(base + UTMIP_TX_CFG0);
468 writel_relaxed(val, base + UTMIP_TX_CFG0);
470 val = readl_relaxed(base + UTMIP_HSRX_CFG0);
474 writel_relaxed(val, base + UTMIP_HSRX_CFG0);
476 val = readl_relaxed(base + UTMIP_HSRX_CFG1);
479 writel_relaxed(val, base + UTMIP_HSRX_CFG1);
481 val = readl_relaxed(base + UTMIP_DEBOUNCE_CFG0);
484 writel_relaxed(val, base + UTMIP_DEBOUNCE_CFG0);
486 val = readl_relaxed(base + UTMIP_MISC_CFG0);
488 writel_relaxed(val, base + UTMIP_MISC_CFG0);
491 val = readl_relaxed(base + UTMIP_MISC_CFG1);
496 writel_relaxed(val, base + UTMIP_MISC_CFG1);
498 val = readl_relaxed(base + UTMIP_PLL_CFG1);
503 writel_relaxed(val, base + UTMIP_PLL_CFG1);
507 val = readl_relaxed(base + USB_SUSP_CTRL);
509 writel_relaxed(val, base + USB_SUSP_CTRL);
511 val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
513 writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
515 val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
517 writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
524 val = readl_relaxed(base + UTMIP_XCVR_CFG0);
542 writel_relaxed(val, base + UTMIP_XCVR_CFG0);
544 val = readl_relaxed(base + UTMIP_XCVR_CFG1);
548 writel_relaxed(val, base + UTMIP_XCVR_CFG1);
550 val = readl_relaxed(base + UTMIP_BIAS_CFG1);
553 writel_relaxed(val, base + UTMIP_BIAS_CFG1);
555 val = readl_relaxed(base + UTMIP_SPARE_CFG0);
560 writel_relaxed(val, base + UTMIP_SPARE_CFG0);
563 val = readl_relaxed(base + USB_SUSP_CTRL);
565 writel_relaxed(val, base + USB_SUSP_CTRL);
568 val = readl_relaxed(base + USB_SUSP_CTRL);
570 writel_relaxed(val, base + USB_SUSP_CTRL);
573 val = readl_relaxed(base + USB1_LEGACY_CTRL);
576 writel_relaxed(val, base + USB1_LEGACY_CTRL);
578 val = readl_relaxed(base + USB_SUSP_CTRL);
580 writel_relaxed(val, base + USB_SUSP_CTRL);
586 val = readl_relaxed(base + USB_USBMODE);
592 writel_relaxed(val, base + USB_USBMODE);
603 void __iomem *base = phy->regs;
609 val = readl_relaxed(base + USB_SUSP_CTRL);
612 writel_relaxed(val, base + USB_SUSP_CTRL);
615 val = readl_relaxed(base + USB_SUSP_CTRL);
617 writel_relaxed(val, base + USB_SUSP_CTRL);
619 val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
621 writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
623 val = readl_relaxed(base + UTMIP_XCVR_CFG0);
626 writel_relaxed(val, base + UTMIP_XCVR_CFG0);
628 val = readl_relaxed(base + UTMIP_XCVR_CFG1);
631 writel_relaxed(val, base + UTMIP_XCVR_CFG1);
638 void __iomem *base = phy->regs;
641 val = readl_relaxed(base + UTMIP_TX_CFG0);
643 writel_relaxed(val, base + UTMIP_TX_CFG0);
648 void __iomem *base = phy->regs;
651 val = readl_relaxed(base + UTMIP_TX_CFG0);
653 writel_relaxed(val, base + UTMIP_TX_CFG0);
659 void __iomem *base = phy->regs;
662 val = readl_relaxed(base + UTMIP_MISC_CFG0);
668 writel_relaxed(val, base + UTMIP_MISC_CFG0);
671 val = readl_relaxed(base + UTMIP_MISC_CFG0);
673 writel_relaxed(val, base + UTMIP_MISC_CFG0);
679 void __iomem *base = phy->regs;
682 val = readl_relaxed(base + UTMIP_MISC_CFG0);
684 writel_relaxed(val, base + UTMIP_MISC_CFG0);
690 void __iomem *base = phy->regs;
706 val = readl_relaxed(base + USB_SUSP_CTRL);
708 writel_relaxed(val, base + USB_SUSP_CTRL);
710 val = readl_relaxed(base + ULPI_TIMING_CTRL_0);
712 writel_relaxed(val, base + ULPI_TIMING_CTRL_0);
714 val = readl_relaxed(base + USB_SUSP_CTRL);
716 writel_relaxed(val, base + USB_SUSP_CTRL);
719 writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
724 writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
730 writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
745 val = readl_relaxed(base + USB_SUSP_CTRL);
747 writel_relaxed(val, base + USB_SUSP_CTRL);
750 val = readl_relaxed(base + USB_SUSP_CTRL);
752 writel_relaxed(val, base + USB_SUSP_CTRL);