Lines Matching defs:base
235 void __iomem *base = mxs_phy->phy.io_priv;
240 phytx = readl(base + HW_USBPHY_TX);
243 writel(phytx, base + HW_USBPHY_TX);
247 static int mxs_phy_pll_enable(void __iomem *base, bool enable)
254 writel(BM_USBPHY_PLL_REG_ENABLE, base + HW_USBPHY_PLL_SIC_SET);
255 writel(BM_USBPHY_PLL_BYPASS, base + HW_USBPHY_PLL_SIC_CLR);
256 writel(BM_USBPHY_PLL_POWER, base + HW_USBPHY_PLL_SIC_SET);
257 ret = readl_poll_timeout(base + HW_USBPHY_PLL_SIC,
263 writel(BM_USBPHY_PLL_EN_USB_CLKS, base +
266 writel(BM_USBPHY_PLL_EN_USB_CLKS, base +
268 writel(BM_USBPHY_PLL_POWER, base + HW_USBPHY_PLL_SIC_CLR);
269 writel(BM_USBPHY_PLL_BYPASS, base + HW_USBPHY_PLL_SIC_SET);
270 writel(BM_USBPHY_PLL_REG_ENABLE, base + HW_USBPHY_PLL_SIC_CLR);
279 void __iomem *base = mxs_phy->phy.io_priv;
282 ret = mxs_phy_pll_enable(base, true);
287 ret = stmp_reset_block(base + HW_USBPHY_CTRL);
292 writel(0, base + HW_USBPHY_PWD);
306 base + HW_USBPHY_CTRL_SET);
309 writel(BM_USBPHY_IP_FIX, base + HW_USBPHY_IP_SET);
330 mxs_phy_pll_enable(base, false);
359 void __iomem *base = mxs_phy->phy.io_priv;
364 base + HW_USBPHY_DEBUG_CLR);
382 base + HW_USBPHY_DEBUG_SET);
674 void __iomem *base = phy->io_priv;
688 base + HW_USBPHY_DEBUG_CLR);
698 base + HW_USBPHY_DEBUG_SET);
706 void __iomem *base;
718 base = devm_platform_ioremap_resource(pdev, 0);
719 if (IS_ERR(base))
720 return PTR_ERR(base);
780 mxs_phy->phy.io_priv = base;