Lines Matching refs:musb_readl
50 rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
52 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
70 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
71 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
73 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
74 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
76 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
77 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
79 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
80 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
82 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
101 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
102 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
110 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
111 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
112 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
119 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
120 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
207 val = musb_readl(fifo, 0);
215 val = musb_readl(fifo, 0);
302 val = musb_readl(fifo, 0);
344 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
367 reg = musb_readl(tbase, TUSB_PRCM_CONF);
408 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
432 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
433 prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
443 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
562 prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
563 conf = musb_readl(tbase, TUSB_DEV_CONF);
580 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
616 musb_readl(tbase, TUSB_DEV_OTG_STAT),
632 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
633 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
634 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
635 dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
667 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
679 u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
828 int_mask = musb_readl(tbase, TUSB_INT_MASK);
831 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
850 reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
859 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
885 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
893 u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
954 if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
1037 if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
1070 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
1074 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);