Lines Matching defs:tbase
46 void __iomem *tbase = musb->ctrl_base;
50 rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
52 die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
63 void __iomem *tbase = musb->ctrl_base;
70 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
71 TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
73 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
74 TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
76 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
77 TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
79 TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
80 TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
82 TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
96 void __iomem *tbase = musb->ctrl_base;
101 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
102 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
105 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
108 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
110 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
111 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
112 } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
115 musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
117 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
119 musb_readl(tbase, TUSB_PHY_OTG_CTRL),
120 musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
328 void __iomem *tbase = musb->ctrl_base;
344 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
352 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
364 void __iomem *tbase = musb->ctrl_base;
367 reg = musb_readl(tbase, TUSB_PRCM_CONF);
378 musb_writel(tbase, TUSB_PRCM_CONF, reg);
391 void __iomem *tbase = musb->ctrl_base;
401 musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
408 reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
418 musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
428 void __iomem *tbase = musb->ctrl_base;
432 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
433 prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
442 musb_writel(tbase, TUSB_PRCM_MNGMT, tmp);
443 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
444 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt);
552 void __iomem *tbase = musb->ctrl_base;
562 prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
563 conf = musb_readl(tbase, TUSB_DEV_CONF);
580 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
608 musb_writel(tbase, TUSB_PRCM_MNGMT, prcm);
609 musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer);
610 musb_writel(tbase, TUSB_DEV_CONF, conf);
616 musb_readl(tbase, TUSB_DEV_OTG_STAT),
629 void __iomem *tbase = musb->ctrl_base;
632 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
633 phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
634 phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
635 dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
661 musb_writel(tbase, TUSB_PHY_OTG_CTRL,
663 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE,
665 musb_writel(tbase, TUSB_DEV_CONF, dev_conf);
667 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
677 tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
679 u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
821 void __iomem *tbase = musb->ctrl_base;
828 int_mask = musb_readl(tbase, TUSB_INT_MASK);
829 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
831 int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
848 musb_writel(tbase, TUSB_SCRATCH_PAD, 0);
849 musb_writel(tbase, TUSB_SCRATCH_PAD, i);
850 reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
859 reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
860 musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg);
878 idle_timeout = tusb_otg_ints(musb, int_src, tbase);
885 u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
888 musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src);
893 u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
895 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src);
907 musb_writel(tbase, TUSB_INT_SRC_CLEAR,
912 musb_writel(tbase, TUSB_INT_MASK, int_mask);
927 void __iomem *tbase = musb->ctrl_base;
931 musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
934 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0);
935 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
936 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
939 musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
940 musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff);
941 musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff);
944 musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
948 musb_writel(tbase, TUSB_INT_CTRL_CONF,
954 if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
956 musb_writel(tbase, TUSB_INT_SRC_SET,
971 void __iomem *tbase = musb->ctrl_base;
976 musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
977 musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff);
978 musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
979 musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
996 void __iomem *tbase = musb->ctrl_base;
1002 musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F);
1005 musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
1008 musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
1012 musb_writel(tbase, TUSB_DMA_REQ_CONF,
1018 musb_writel(tbase, TUSB_WAIT_COUNT, 1);
1023 void __iomem *tbase = musb->ctrl_base;
1037 if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
1053 musb_writel(tbase, TUSB_VLYNQ_CTRL, 8);
1061 musb_writel(tbase, TUSB_PRCM_MNGMT,
1070 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
1072 musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg);
1074 reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
1076 musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg);