Lines Matching refs:tibase
157 void __iomem *tibase;
176 tibase = controller->tibase;
186 tx = tibase + DAVINCI_TXCPPI_STATERAM_OFFSET(i);
196 rx = tibase + DAVINCI_RXCPPI_STATERAM_OFFSET(i);
202 musb_writel(tibase, DAVINCI_TXCPPI_INTENAB_REG,
204 musb_writel(tibase, DAVINCI_RXCPPI_INTENAB_REG,
208 musb_writel(tibase, DAVINCI_TXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_ENABLE);
209 musb_writel(tibase, DAVINCI_RXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_ENABLE);
212 musb_writel(tibase, DAVINCI_RNDIS_REG, 0);
213 musb_writel(tibase, DAVINCI_AUTOREQ_REG, 0);
224 void __iomem *tibase;
230 tibase = controller->tibase;
232 musb_writel(tibase, DAVINCI_TXCPPI_INTCLR_REG,
234 musb_writel(tibase, DAVINCI_RXCPPI_INTCLR_REG,
251 musb_writel(tibase, DAVINCI_TXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_DISABLE);
252 musb_writel(tibase, DAVINCI_RXCPPI_CTRL_REG, DAVINCI_DMA_CTRL_DISABLE);
263 static inline void core_rxirq_disable(void __iomem *tibase, unsigned epnum)
265 musb_writel(tibase, DAVINCI_USB_INT_MASK_CLR_REG, 1 << (epnum + 8));
268 static inline void core_rxirq_enable(void __iomem *tibase, unsigned epnum)
270 musb_writel(tibase, DAVINCI_USB_INT_MASK_SET_REG, 1 << (epnum + 8));
287 void __iomem *tibase;
291 tibase = controller->tibase;
312 core_rxirq_disable(tibase, ep->epnum);
333 void __iomem *tibase;
338 tibase = c->controller->tibase;
343 core_rxirq_enable(tibase, c->index + 1);
364 musb_readl(c->controller->tibase,
411 void __iomem *tibase, int is_rndis)
415 u32 value = musb_readl(tibase, DAVINCI_RNDIS_REG);
424 musb_writel(tibase, DAVINCI_RNDIS_REG, value);
454 void __iomem *tibase, int onepacket, unsigned n_bds)
463 tmp = musb_readl(tibase, DAVINCI_AUTOREQ_REG);
484 musb_writel(tibase, DAVINCI_AUTOREQ_REG, val);
486 tmp = musb_readl(tibase, DAVINCI_AUTOREQ_REG);
770 void __iomem *tibase = musb->ctrl_base;
809 n_bds = cppi_autoreq_update(rx, tibase, onepacket, n_bds);
822 musb_readl(tibase,
895 core_rxirq_enable(tibase, rx->index + 1);
909 i = musb_readl(tibase,
914 musb_writel(tibase,
918 musb_writel(tibase,
922 i = musb_readl(tibase,
928 musb_writel(tibase,
1145 void __iomem *tibase;
1155 tibase = musb->ctrl_base;
1157 tx = musb_readl(tibase, DAVINCI_TXCPPI_MASKED_REG);
1158 rx = musb_readl(tibase, DAVINCI_RXCPPI_MASKED_REG);
1283 core_rxirq_disable(tibase, index + 1);
1289 musb_writel(tibase, DAVINCI_CPPI_EOI_REG, 0);
1312 controller->tibase = mregs - DAVINCI_BASE_OFFSET;
1377 void __iomem *tibase;
1405 tibase = controller->tibase;
1425 value = musb_readl(tibase, DAVINCI_TXCPPI_TEAR_REG);
1427 musb_writel(tibase, DAVINCI_TXCPPI_TEAR_REG, cppi_ch->index);
1469 core_rxirq_disable(tibase, cppi_ch->index + 1);
1473 value = musb_readl(tibase, DAVINCI_AUTOREQ_REG);
1475 musb_writel(tibase, DAVINCI_AUTOREQ_REG, value);