Lines Matching refs:temp
134 u32 temp;
137 temp = readl(&xhci->op_regs->command);
138 temp |= (CMD_RUN);
140 temp);
141 writel(temp, &xhci->op_regs->command);
488 u32 temp;
495 temp = readl(rhub->ports[i]->addr);
496 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
644 u32 temp;
670 temp = readl(&xhci->ir_set->irq_control);
671 temp &= ~ER_IRQ_INTERVAL_MASK;
672 temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
673 writel(temp, &xhci->ir_set->irq_control);
676 temp = readl(&xhci->op_regs->command);
677 temp |= (CMD_EIE);
679 "// Enable interrupts, cmd = 0x%x.", temp);
680 writel(temp, &xhci->op_regs->command);
682 temp = readl(&xhci->ir_set->irq_pending);
685 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
686 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
724 u32 temp;
760 temp = readl(&xhci->op_regs->status);
761 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
762 temp = readl(&xhci->ir_set->irq_pending);
763 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1111 u32 command, temp = 0;
1173 temp = readl(&xhci->op_regs->status);
1176 if (temp & (STS_SRE | STS_HCE)) {
1179 xhci_warn(xhci, "xHC error in resume, USBSTS 0x%x, Reinit\n", temp);
1204 temp = readl(&xhci->op_regs->status);
1205 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1206 temp = readl(&xhci->ir_set->irq_pending);
1207 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1653 u32 temp;
1686 temp = readl(&xhci->op_regs->status);
1687 if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {