Lines Matching refs:op_regs
95 halted = readl(&xhci->op_regs->status) & STS_HALT;
99 cmd = readl(&xhci->op_regs->command);
101 writel(cmd, &xhci->op_regs->command);
118 ret = xhci_handshake(&xhci->op_regs->status,
137 temp = readl(&xhci->op_regs->command);
141 writel(temp, &xhci->op_regs->command);
147 ret = xhci_handshake(&xhci->op_regs->status,
175 state = readl(&xhci->op_regs->status);
188 command = readl(&xhci->op_regs->command);
190 writel(command, &xhci->op_regs->command);
202 ret = xhci_handshake(&xhci->op_regs->command, CMD_RESET, 0, timeout_us);
215 ret = xhci_handshake(&xhci->op_regs->status, STS_CNR, 0, timeout_us);
257 val = readl(&xhci->op_regs->command);
259 writel(val, &xhci->op_regs->command);
262 val = readl(&xhci->op_regs->status);
264 writel(val, &xhci->op_regs->status);
267 val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
269 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
270 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
272 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
290 err = xhci_handshake(&xhci->op_regs->status,
676 temp = readl(&xhci->op_regs->command);
680 writel(temp, &xhci->op_regs->command);
760 temp = readl(&xhci->op_regs->status);
761 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
770 readl(&xhci->op_regs->status));
818 readl(&xhci->op_regs->status));
825 xhci->s3.command = readl(&xhci->op_regs->command);
826 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
827 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
828 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
838 writel(xhci->s3.command, &xhci->op_regs->command);
839 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
840 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
841 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
854 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
863 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
961 status = readl(&xhci->op_regs->status);
1036 command = readl(&xhci->op_regs->command);
1038 writel(command, &xhci->op_regs->command);
1043 if (xhci_handshake(&xhci->op_regs->status,
1055 command = readl(&xhci->op_regs->command);
1057 writel(command, &xhci->op_regs->command);
1059 if (xhci_handshake(&xhci->op_regs->status,
1070 res = readl(&xhci->op_regs->status);
1143 retval = xhci_handshake(&xhci->op_regs->status,
1157 command = readl(&xhci->op_regs->command);
1159 writel(command, &xhci->op_regs->command);
1165 if (xhci_handshake(&xhci->op_regs->status,
1173 temp = readl(&xhci->op_regs->status);
1204 temp = readl(&xhci->op_regs->status);
1205 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1213 readl(&xhci->op_regs->status));
1242 command = readl(&xhci->op_regs->command);
1244 writel(command, &xhci->op_regs->command);
1245 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1686 temp = readl(&xhci->op_regs->status);
3979 state = readl(&xhci->op_regs->status);
4271 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
5285 xhci->op_regs = hcd->regs +