Lines Matching refs:ir_set
275 ARRAY_SIZE(xhci->run_regs->ir_set));
280 ir = &xhci->run_regs->ir_set[i];
663 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
670 temp = readl(&xhci->ir_set->irq_control);
673 writel(temp, &xhci->ir_set->irq_control);
682 temp = readl(&xhci->ir_set->irq_pending);
685 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
686 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
762 temp = readl(&xhci->ir_set->irq_pending);
763 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
829 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
830 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
831 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
832 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
833 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
842 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
843 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
844 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
845 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
846 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
1206 temp = readl(&xhci->ir_set->irq_pending);
1207 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);