Lines Matching refs:ports
170 struct usb_hub_descriptor *desc, int ports)
176 desc->bNbrPorts = ports;
186 /* Bits 6:5 - no TTs in root ports */
195 int ports;
203 ports = rhub->num_ports;
204 xhci_common_hub_descriptor(xhci, desc, ports);
206 temp = 1 + (ports / 8);
214 for (i = 0; i < ports; i++) {
215 portsc = readl(rhub->ports[i]->addr);
227 * ports on it. The USB 2.0 specification says that there are two
230 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
234 * set of ports that actually exist.
241 for (i = 0; i < (ports + 1 + 7) / 8; i++)
250 int ports;
257 ports = rhub->num_ports;
258 xhci_common_hub_descriptor(xhci, desc, ports);
271 for (i = 0; i < ports; i++) {
272 portsc = readl(rhub->ports[i]->addr);
328 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
484 /* Don't allow the USB core to disable SuperSpeed ports. */
578 port = rhub->ports[index];
610 /* xhci only supports test mode for usb2 ports */
611 port = xhci->usb2_rhub.ports[wIndex];
640 /* Put all ports to the Disable state by clear PP */
642 /* Power off USB3 ports*/
645 /* Power off USB2 ports*/
796 * This Function verifies if all xhc USB3 ports have entered U0, if so,
814 "All USB3 ports have entered U0 already!");
1055 port = rhub->ports[wIndex];
1107 struct xhci_port **ports;
1112 ports = rhub->ports;
1153 port = ports[portnum1 - 1];
1198 port = ports[portnum1 - 1];
1386 * Turn on ports, even if there isn't per-port switching.
1448 port = ports[portnum1 - 1];
1545 struct xhci_port **ports;
1548 ports = rhub->ports;
1579 temp = readl(ports[i]->addr);
1589 (ports[i]->resume_timestamp && time_after_eq(
1590 jiffies, ports[i]->resume_timestamp))) {
1616 struct xhci_port **ports;
1621 ports = rhub->ports;
1637 * Prepare ports for suspend, but don't write anything before all ports
1646 t1 = readl(ports[port_index]->addr);
1670 /* suspend ports in U0, or bail out for new connect changes */
1711 /* write port settings, stopping and suspending ports if needed */
1727 writel(portsc_buf[port_index], ports[port_index]->addr);
1778 struct xhci_port **ports;
1781 ports = rhub->ports;
1799 /* bus specific resume for ports we suspended at bus_suspend */
1807 portsc = readl(ports[port_index]->addr);
1809 /* warm reset CAS limited ports stuck in polling/compliance */
1812 xhci_port_missing_cas_quirk(ports[port_index])) {
1835 /* disable wake for all ports, write new link state if needed */
1837 writel(portsc, ports[port_index]->addr);
1850 xhci_test_and_clear_bit(xhci, ports[port_index],
1852 xhci_set_link_state(xhci, ports[port_index], XDEV_U0);
1858 sret = xhci_handshake(ports[port_index]->addr, PORT_PLC,
1865 xhci_test_and_clear_bit(xhci, ports[port_index], PORT_PLC);
1888 return rhub->bus_state.resuming_ports; /* USB2 ports only */