Lines Matching defs:temp
60 u32 temp;
99 temp = readl(&xhci->cap_regs->hcc_params);
100 if (HCC_LTC(temp))
105 temp = readl(&xhci->cap_regs->hcs_params3);
106 buf[12] = HCS_U1_LATENCY(temp);
107 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
172 u16 temp;
177 temp = 0;
180 temp |= HUB_CHAR_INDV_PORT_LPSM;
182 temp |= HUB_CHAR_NO_LPSM;
185 temp |= HUB_CHAR_INDV_PORT_OCPM;
188 desc->wHubCharacteristics = cpu_to_le16(temp);
196 u16 temp;
206 temp = 1 + (ports / 8);
207 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
575 u32 temp;
579 temp = readl(port->addr);
582 hcd->self.busnum, index + 1, on ? "ON" : "OFF", temp);
584 temp = xhci_port_state_to_neutral(temp);
588 writel(temp | PORT_POWER, port->addr);
592 writel(temp & ~PORT_POWER, port->addr);
596 temp = usb_acpi_power_manageable(hcd->self.root_hub,
598 if (temp)
607 u32 temp;
612 temp = readl(port->addr + PORTPMSC);
613 temp |= test_mode << PORT_TEST_MODE_SHIFT;
614 writel(temp, port->addr + PORTPMSC);
685 u32 temp;
689 temp = xhci_port_state_to_neutral(portsc);
690 temp &= ~PORT_PLS_MASK;
691 temp |= PORT_LINK_STROBE | link_state;
692 writel(temp, port->addr);
696 portsc, temp);
702 u32 temp;
704 temp = readl(port->addr);
705 temp = xhci_port_state_to_neutral(temp);
708 temp |= PORT_WKCONN_E;
710 temp &= ~PORT_WKCONN_E;
713 temp |= PORT_WKDISC_E;
715 temp &= ~PORT_WKDISC_E;
718 temp |= PORT_WKOC_E;
720 temp &= ~PORT_WKOC_E;
722 writel(temp, port->addr);
729 u32 temp;
731 temp = readl(port->addr);
732 if (temp & port_bit) {
733 temp = xhci_port_state_to_neutral(temp);
734 temp |= port_bit;
735 writel(temp, port->addr);
1098 u32 temp, status;
1154 temp = readl(port->addr);
1155 if (temp == ~(u32)0) {
1160 trace_xhci_get_port_status(wIndex, temp);
1161 status = xhci_get_port_status(hcd, bus_state, wIndex, temp,
1167 hcd->self.busnum, portnum1, temp, status);
1180 status = xhci_get_ext_port_status(temp, port_li);
1200 temp = readl(port->addr);
1201 if (temp == ~(u32)0) {
1206 temp = xhci_port_state_to_neutral(temp);
1210 temp = readl(port->addr);
1211 if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1222 temp = readl(port->addr);
1223 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1224 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1247 temp = readl(port->addr);
1251 temp = readl(port->addr);
1256 temp = xhci_port_state_to_neutral(temp);
1261 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1264 writel(temp | PORT_PE, port->addr);
1265 temp = readl(port->addr);
1274 temp = readl(port->addr);
1298 if ((temp & PORT_CONNECT)) {
1307 temp = readl(port->addr);
1311 if (!(temp & PORT_PE)) {
1330 u32 pls = temp & PORT_PLS_MASK;
1355 temp = readl(port->addr);
1375 temp = readl(port->addr);
1376 if ((temp & PORT_PLS_MASK) == XDEV_U3)
1380 temp = readl(port->addr);
1394 temp = (temp | PORT_RESET);
1395 writel(temp, port->addr);
1397 temp = readl(port->addr);
1399 hcd->self.busnum, portnum1, temp);
1403 temp = readl(port->addr);
1405 hcd->self.busnum, portnum1, temp);
1408 temp |= PORT_WR;
1409 writel(temp, port->addr);
1410 temp = readl(port->addr);
1415 temp = readl(port->addr + PORTPMSC);
1416 temp &= ~PORT_U1_TIMEOUT_MASK;
1417 temp |= PORT_U1_TIMEOUT(timeout);
1418 writel(temp, port->addr + PORTPMSC);
1423 temp = readl(port->addr + PORTPMSC);
1424 temp &= ~PORT_U2_TIMEOUT_MASK;
1425 temp |= PORT_U2_TIMEOUT(timeout);
1426 writel(temp, port->addr + PORTPMSC);
1442 temp = readl(port->addr);
1451 temp = readl(port->addr);
1452 if (temp == ~(u32)0) {
1458 temp = xhci_port_state_to_neutral(temp);
1461 temp = readl(port->addr);
1463 xhci_dbg(xhci, "PORTSC %04x\n", temp);
1464 if (temp & PORT_RESET)
1466 if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1467 if ((temp & PORT_PE) == 0)
1501 port->addr, temp);
1505 port->addr, temp);
1537 u32 temp, status;
1579 temp = readl(ports[i]->addr);
1580 if (temp == ~(u32)0) {
1585 trace_xhci_hub_status_data(i, temp);
1587 if ((temp & mask) != 0 ||
1594 if ((temp & PORT_RC))
1596 if (temp & PORT_OC)
1776 u32 temp, portsc;
1795 temp = readl(&xhci->op_regs->command);
1796 temp &= ~CMD_EIE;
1797 writel(temp, &xhci->op_regs->command);
1874 temp = readl(&xhci->op_regs->command);
1875 temp |= CMD_EIE;
1876 writel(temp, &xhci->op_regs->command);
1877 temp = readl(&xhci->op_regs->command);