Lines Matching refs:status
136 * bits in the port status and control registers.
340 * the RD status bit will never get set. Without RD, the controller
393 * Clear stale status bits on Aspeed as we get a stale HCH
453 unsigned short status;
456 * Read the interrupt status, and write it back to clear the
458 * "HC Halted" status bit is persistent: it is RO, not R/WC.
460 status = uhci_readw(uhci, USBSTS);
461 if (!(status & ~USBSTS_HCH)) /* shared interrupt, not mine */
463 uhci_writew(uhci, status, USBSTS); /* Clear it */
469 if (status & ~(USBSTS_USBINT | USBSTS_ERROR | USBSTS_RD)) {
470 if (status & USBSTS_HSE)
473 if (status & USBSTS_HCPE)
476 if (status & USBSTS_HCH) {
496 if (status & USBSTS_RD) {
819 * status and control register is always set to 1. So we try to