Lines Matching refs:ep0state
567 dev->ep0state = EP0_IDLE;
887 switch (dev->ep0state) {
904 dev->ep0state = EP0_END_XFER;
919 DMSG("ep0 i/o, odd state %d\n", dev->ep0state);
1034 ep->dev->ep0state = EP0_STALL;
1386 dev->ep0state = EP0_IDLE;
1618 if (dev->ep0state == EP0_STALL
1653 if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) {
1659 switch (dev->ep0state) {
1735 dev->ep0state = EP0_IN_DATA_PHASE;
1737 dev->ep0state = EP0_OUT_DATA_PHASE;
1764 dev->ep0state = EP0_STALL;
1768 if (likely(dev->ep0state == EP0_IN_DATA_PHASE