Lines Matching refs:ep
175 #define PCH_UDC_CSR(ep) (UDC_CSR_ADDR + ep*4)
182 #define UDC_EPIN_IDX(ep) (ep * 2)
183 #define UDC_EPOUT_IDX(ep) (ep * 2 + 1)
271 * @ep: embedded ep request
277 * @offset_addr: offset address of ep register
278 * @desc: for this ep
286 struct usb_ep ep;
321 * @ep: array of endpoints
343 struct pch_udc_ep ep[PCH_UDC_EP_NUM];
380 * @req: embedded ep request
431 static inline u32 pch_udc_ep_readl(struct pch_udc_ep *ep, unsigned long reg)
433 return ioread32(ep->dev->base_addr + ep->offset_addr + reg);
436 static inline void pch_udc_ep_writel(struct pch_udc_ep *ep,
439 iowrite32(val, ep->dev->base_addr + ep->offset_addr + reg);
442 static inline void pch_udc_ep_bit_set(struct pch_udc_ep *ep,
446 pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) | bitmask, reg);
449 static inline void pch_udc_ep_bit_clr(struct pch_udc_ep *ep,
453 pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) & ~(bitmask), reg);
476 * @ep: end-point number
479 unsigned int ep)
481 unsigned long reg = PCH_UDC_CSR(ep);
491 * @ep: end-point number
495 static u32 pch_udc_read_csr(struct pch_udc_dev *dev, unsigned int ep)
497 unsigned long reg = PCH_UDC_CSR(ep);
621 * @ep: Reference to structure of type pch_udc_ep_regs
623 static void pch_udc_ep_set_stall(struct pch_udc_ep *ep)
625 if (ep->in) {
626 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
627 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
629 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
635 * @ep: Reference to structure of type pch_udc_ep_regs
637 static inline void pch_udc_ep_clear_stall(struct pch_udc_ep *ep)
640 pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
642 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
647 * @ep: Reference to structure of type pch_udc_ep_regs
650 static inline void pch_udc_ep_set_trfr_type(struct pch_udc_ep *ep,
653 pch_udc_ep_writel(ep, ((type << UDC_EPCTL_ET_SHIFT) &
659 * @ep: Reference to structure of type pch_udc_ep_regs
663 static void pch_udc_ep_set_bufsz(struct pch_udc_ep *ep,
668 data = pch_udc_ep_readl(ep, UDC_BUFIN_FRAMENUM_ADDR);
670 pch_udc_ep_writel(ep, data, UDC_BUFIN_FRAMENUM_ADDR);
672 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
674 pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
680 * @ep: Reference to structure of type pch_udc_ep_regs
683 static void pch_udc_ep_set_maxpkt(struct pch_udc_ep *ep, u32 pkt_size)
685 u32 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
687 pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
692 * @ep: Reference to structure of type pch_udc_ep_regs
695 static inline void pch_udc_ep_set_subptr(struct pch_udc_ep *ep, u32 addr)
697 pch_udc_ep_writel(ep, addr, UDC_SUBPTR_ADDR);
702 * @ep: Reference to structure of type pch_udc_ep_regs
705 static inline void pch_udc_ep_set_ddptr(struct pch_udc_ep *ep, u32 addr)
707 pch_udc_ep_writel(ep, addr, UDC_DESPTR_ADDR);
712 * @ep: Reference to structure of type pch_udc_ep_regs
714 static inline void pch_udc_ep_set_pd(struct pch_udc_ep *ep)
716 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_P);
721 * @ep: Reference to structure of type pch_udc_ep_regs
723 static inline void pch_udc_ep_set_rrdy(struct pch_udc_ep *ep)
725 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
730 * @ep: Reference to structure of type pch_udc_ep_regs
732 static inline void pch_udc_ep_clear_rrdy(struct pch_udc_ep *ep)
734 pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
877 * @ep: Reference to structure of type pch_udc_ep_regs
880 static inline u32 pch_udc_read_ep_control(struct pch_udc_ep *ep)
882 return pch_udc_ep_readl(ep, UDC_EPCTL_ADDR);
887 * @ep: Reference to structure of type pch_udc_ep_regs
890 static inline void pch_udc_clear_ep_control(struct pch_udc_ep *ep)
892 return pch_udc_ep_writel(ep, 0, UDC_EPCTL_ADDR);
897 * @ep: Reference to structure of type pch_udc_ep_regs
900 static inline u32 pch_udc_read_ep_status(struct pch_udc_ep *ep)
902 return pch_udc_ep_readl(ep, UDC_EPSTS_ADDR);
907 * @ep: Reference to structure of type pch_udc_ep_regs
910 static inline void pch_udc_clear_ep_status(struct pch_udc_ep *ep,
913 return pch_udc_ep_writel(ep, stat, UDC_EPSTS_ADDR);
919 * @ep: Reference to structure of type pch_udc_ep_regs
921 static inline void pch_udc_ep_set_nak(struct pch_udc_ep *ep)
923 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_SNAK);
929 * @ep: reference to structure of type pch_udc_ep_regs
931 static void pch_udc_ep_clear_nak(struct pch_udc_ep *ep)
934 struct pch_udc_dev *dev = ep->dev;
936 if (!(pch_udc_ep_readl(ep, UDC_EPCTL_ADDR) & UDC_EPCTL_NAK))
938 if (!ep->in) {
940 while (!(pch_udc_read_ep_status(ep) & UDC_EPSTS_MRXFIFO_EMP) &&
948 while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_NAK) && --loopcnt) {
949 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
953 dev_err(&dev->pdev->dev, "%s: Clear NAK not set for ep%d%s\n",
954 __func__, ep->num, (ep->in ? "in" : "out"));
959 * @ep: reference to structure of type pch_udc_ep_regs
964 static void pch_udc_ep_fifo_flush(struct pch_udc_ep *ep, int dir)
966 if (dir) { /* IN ep */
967 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
974 * @ep: reference to structure of type pch_udc_ep_regs
978 static void pch_udc_ep_enable(struct pch_udc_ep *ep,
985 pch_udc_ep_set_trfr_type(ep, desc->bmAttributes);
986 if (ep->in)
990 pch_udc_ep_set_bufsz(ep, buff_size, ep->in);
991 pch_udc_ep_set_maxpkt(ep, usb_endpoint_maxp(desc));
992 pch_udc_ep_set_nak(ep);
993 pch_udc_ep_fifo_flush(ep, ep->in);
995 val = ep->num << UDC_CSR_NE_NUM_SHIFT | ep->in << UDC_CSR_NE_DIR_SHIFT |
1003 if (ep->in)
1004 pch_udc_write_csr(ep->dev, val, UDC_EPIN_IDX(ep->num));
1006 pch_udc_write_csr(ep->dev, val, UDC_EPOUT_IDX(ep->num));
1011 * @ep: reference to structure of type pch_udc_ep_regs
1013 static void pch_udc_ep_disable(struct pch_udc_ep *ep)
1015 if (ep->in) {
1017 pch_udc_ep_writel(ep, UDC_EPCTL_F, UDC_EPCTL_ADDR);
1019 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
1020 pch_udc_ep_bit_set(ep, UDC_EPSTS_ADDR, UDC_EPSTS_IN);
1023 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
1026 pch_udc_ep_writel(ep, 0, UDC_DESPTR_ADDR);
1031 * @ep: reference to structure of type pch_udc_ep_regs
1033 static void pch_udc_wait_ep_stall(struct pch_udc_ep *ep)
1038 while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_S) && --count)
1041 dev_err(&ep->dev->pdev->dev, "%s: wait error\n", __func__);
1065 /* mask and clear all ep interrupts */
1091 /* mask all ep interrupts */
1463 * @ep: Reference to the endpoint structure
1467 static void complete_req(struct pch_udc_ep *ep, struct pch_udc_request *req,
1473 unsigned halted = ep->halted;
1483 dev = ep->dev;
1486 if (ep->in)
1496 if (ep->in)
1511 ep->halted = 1;
1513 if (!ep->in)
1514 pch_udc_ep_clear_rrdy(ep);
1515 usb_gadget_giveback_request(&ep->ep, &req->req);
1517 ep->halted = halted;
1522 * @ep: Reference to the endpoint structure
1524 static void empty_req_queue(struct pch_udc_ep *ep)
1528 ep->halted = 1;
1529 while (!list_empty(&ep->queue)) {
1530 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1531 complete_req(ep, req, -ESHUTDOWN); /* Remove from list */
1566 * @ep: Reference to the endpoint structure
1575 static int pch_udc_create_dma_chain(struct pch_udc_ep *ep,
1586 pch_udc_free_dma_chain(ep->dev, req);
1599 td = dma_pool_alloc(ep->dev->data_requests, gfp_flags,
1617 pch_udc_free_dma_chain(ep->dev, req);
1626 * @ep: Reference to the endpoint structure
1634 static int prepare_dma(struct pch_udc_ep *ep, struct pch_udc_request *req,
1640 retval = pch_udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
1645 if (ep->in)
1654 * @ep: Reference to the endpoint structure
1657 static void process_zlp(struct pch_udc_ep *ep, struct pch_udc_request *req)
1659 struct pch_udc_dev *dev = ep->dev;
1662 complete_req(ep, req, 0);
1673 pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
1680 * @ep: Reference to the endpoint structure
1683 static void pch_udc_start_rxrequest(struct pch_udc_ep *ep,
1688 pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
1699 pch_udc_ep_set_ddptr(ep, req->td_data_phys);
1701 pch_udc_enable_ep_interrupts(ep->dev, UDC_EPINT_OUT_EP0 << ep->num);
1702 pch_udc_set_dma(ep->dev, DMA_DIR_RX);
1703 pch_udc_ep_clear_nak(ep);
1704 pch_udc_ep_set_rrdy(ep);
1721 struct pch_udc_ep *ep;
1729 ep = container_of(usbep, struct pch_udc_ep, ep);
1730 dev = ep->dev;
1734 ep->ep.desc = desc;
1735 ep->halted = 0;
1736 pch_udc_ep_enable(ep, &ep->dev->cfg_data, desc);
1737 ep->ep.maxpacket = usb_endpoint_maxp(desc);
1738 pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1754 struct pch_udc_ep *ep;
1760 ep = container_of(usbep, struct pch_udc_ep, ep);
1761 if ((usbep->name == ep0_string) || !ep->ep.desc)
1764 spin_lock_irqsave(&ep->dev->lock, iflags);
1765 empty_req_queue(ep);
1766 ep->halted = 1;
1767 pch_udc_ep_disable(ep);
1768 pch_udc_disable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1769 ep->ep.desc = NULL;
1770 INIT_LIST_HEAD(&ep->queue);
1771 spin_unlock_irqrestore(&ep->dev->lock, iflags);
1789 struct pch_udc_ep *ep;
1794 ep = container_of(usbep, struct pch_udc_ep, ep);
1801 if (!ep->dev->dma_addr)
1804 dma_desc = dma_pool_alloc(ep->dev->data_requests, gfp,
1828 struct pch_udc_ep *ep;
1834 ep = container_of(usbep, struct pch_udc_ep, ep);
1836 dev = ep->dev;
1842 pch_udc_free_dma_chain(ep->dev, req);
1843 dma_pool_free(ep->dev->data_requests, req->td_data,
1864 struct pch_udc_ep *ep;
1871 ep = container_of(usbep, struct pch_udc_ep, ep);
1872 dev = ep->dev;
1873 if (!ep->ep.desc && ep->num)
1885 if (ep->in)
1901 if (ep->in) {
1916 retval = prepare_dma(ep, req, GFP_ATOMIC);
1923 if (list_empty(&ep->queue) && !ep->halted) {
1926 process_zlp(ep, req);
1930 if (!ep->in) {
1931 pch_udc_start_rxrequest(ep, req);
1938 pch_udc_wait_ep_stall(ep);
1939 pch_udc_ep_clear_nak(ep);
1940 pch_udc_enable_ep_interrupts(ep->dev, (1 << ep->num));
1943 /* Now add this request to the ep's pending requests */
1945 list_add_tail(&req->queue, &ep->queue);
1965 struct pch_udc_ep *ep;
1970 ep = container_of(usbep, struct pch_udc_ep, ep);
1971 if (!usbep || !usbreq || (!ep->ep.desc && ep->num))
1974 spin_lock_irqsave(&ep->dev->lock, flags);
1976 list_for_each_entry(req, &ep->queue, queue) {
1978 pch_udc_ep_set_nak(ep);
1980 complete_req(ep, req, -ECONNRESET);
1985 spin_unlock_irqrestore(&ep->dev->lock, flags);
2001 struct pch_udc_ep *ep;
2007 ep = container_of(usbep, struct pch_udc_ep, ep);
2008 if (!ep->ep.desc && !ep->num)
2010 if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
2013 if (list_empty(&ep->queue)) {
2015 if (ep->num == PCH_UDC_EP0)
2016 ep->dev->stall = 1;
2017 pch_udc_ep_set_stall(ep);
2019 ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
2021 pch_udc_ep_clear_stall(ep);
2042 struct pch_udc_ep *ep;
2048 ep = container_of(usbep, struct pch_udc_ep, ep);
2049 if (!ep->ep.desc && !ep->num)
2051 if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
2054 if (!list_empty(&ep->queue)) {
2057 if (ep->num == PCH_UDC_EP0)
2058 ep->dev->stall = 1;
2059 pch_udc_ep_set_stall(ep);
2060 pch_udc_enable_ep_interrupts(ep->dev,
2061 PCH_UDC_EPINT(ep->in, ep->num));
2062 ep->dev->prot_stall = 1;
2075 struct pch_udc_ep *ep;
2080 ep = container_of(usbep, struct pch_udc_ep, ep);
2081 if (ep->ep.desc || !ep->num)
2082 pch_udc_ep_fifo_flush(ep, ep->in);
2116 * @ep: Reference to the endpoint structure
2118 static void pch_udc_start_next_txrequest(struct pch_udc_ep *ep)
2123 if (pch_udc_read_ep_control(ep) & UDC_EPCTL_P)
2126 if (list_empty(&ep->queue))
2130 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2135 pch_udc_wait_ep_stall(ep);
2137 pch_udc_ep_set_ddptr(ep, 0);
2146 pch_udc_ep_set_ddptr(ep, req->td_data_phys);
2147 pch_udc_set_dma(ep->dev, DMA_DIR_TX);
2148 pch_udc_ep_set_pd(ep);
2149 pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
2150 pch_udc_ep_clear_nak(ep);
2155 * @ep: Reference to the endpoint structure
2157 static void pch_udc_complete_transfer(struct pch_udc_ep *ep)
2160 struct pch_udc_dev *dev = ep->dev;
2162 if (list_empty(&ep->queue))
2164 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2173 (int)(ep->epsts));
2180 complete_req(ep, req, 0);
2182 if (!list_empty(&ep->queue)) {
2183 pch_udc_wait_ep_stall(ep);
2184 pch_udc_ep_clear_nak(ep);
2185 pch_udc_enable_ep_interrupts(ep->dev,
2186 PCH_UDC_EPINT(ep->in, ep->num));
2188 pch_udc_disable_ep_interrupts(ep->dev,
2189 PCH_UDC_EPINT(ep->in, ep->num));
2195 * @ep: Reference to the endpoint structure
2197 static void pch_udc_complete_receiver(struct pch_udc_ep *ep)
2200 struct pch_udc_dev *dev = ep->dev;
2205 if (list_empty(&ep->queue))
2208 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2209 pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
2210 pch_udc_ep_set_ddptr(ep, 0);
2222 (int)(ep->epsts));
2245 complete_req(ep, req, 0);
2247 if (!list_empty(&ep->queue)) {
2248 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2249 pch_udc_start_rxrequest(ep, req);
2262 struct pch_udc_ep *ep;
2264 ep = &dev->ep[UDC_EPIN_IDX(ep_num)];
2265 epsts = ep->epsts;
2266 ep->epsts = 0;
2277 pch_udc_ep_set_stall(ep);
2278 pch_udc_enable_ep_interrupts(ep->dev,
2279 PCH_UDC_EPINT(ep->in, ep->num));
2283 pch_udc_ep_clear_stall(ep);
2285 pch_udc_ep_set_stall(ep);
2286 pch_udc_enable_ep_interrupts(ep->dev,
2287 PCH_UDC_EPINT(ep->in, ep->num));
2291 pch_udc_complete_transfer(ep);
2295 pch_udc_start_next_txrequest(ep);
2306 struct pch_udc_ep *ep;
2309 ep = &dev->ep[UDC_EPOUT_IDX(ep_num)];
2310 epsts = ep->epsts;
2311 ep->epsts = 0;
2313 if ((epsts & UDC_EPSTS_BNA) && (!list_empty(&ep->queue))) {
2315 req = list_entry(ep->queue.next, struct pch_udc_request,
2320 pch_udc_start_rxrequest(ep, req);
2327 pch_udc_ep_set_stall(ep);
2328 pch_udc_enable_ep_interrupts(ep->dev,
2329 PCH_UDC_EPINT(ep->in, ep->num));
2333 pch_udc_ep_clear_stall(ep);
2335 pch_udc_ep_set_stall(ep);
2336 pch_udc_enable_ep_interrupts(ep->dev,
2337 PCH_UDC_EPINT(ep->in, ep->num));
2342 if (ep->dev->prot_stall == 1) {
2343 pch_udc_ep_set_stall(ep);
2344 pch_udc_enable_ep_interrupts(ep->dev,
2345 PCH_UDC_EPINT(ep->in, ep->num));
2347 pch_udc_complete_receiver(ep);
2350 if (list_empty(&ep->queue))
2376 struct pch_udc_ep *ep;
2379 ep = &dev->ep[UDC_EP0IN_IDX];
2380 ep_out = &dev->ep[UDC_EP0OUT_IDX];
2381 epsts = ep->epsts;
2382 ep->epsts = 0;
2393 pch_udc_complete_transfer(ep);
2405 pch_udc_start_next_txrequest(ep);
2419 struct pch_udc_ep *ep;
2421 ep = &dev->ep[UDC_EP0OUT_IDX];
2422 stat = ep->epsts;
2423 ep->epsts = 0;
2429 dev->ep[UDC_EP0IN_IDX].halted = 0;
2430 dev->ep[UDC_EP0OUT_IDX].halted = 0;
2431 dev->setup_data = ep->td_stp->request;
2432 pch_udc_init_setup_buff(ep->td_stp);
2434 pch_udc_ep_fifo_flush(&(dev->ep[UDC_EP0IN_IDX]),
2435 dev->ep[UDC_EP0IN_IDX].in);
2437 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2439 dev->gadget.ep0 = &ep->ep;
2448 ep->td_data->status = (ep->td_data->status &
2451 pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2456 pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
2461 pch_udc_ep_clear_nak(ep);
2465 pch_udc_ep_set_stall(&(dev->ep[UDC_EP0IN_IDX]));
2466 pch_udc_enable_ep_interrupts(ep->dev,
2467 PCH_UDC_EPINT(ep->in, ep->num));
2476 pch_udc_ep_set_ddptr(ep, 0);
2477 if (!list_empty(&ep->queue)) {
2478 ep->epsts = stat;
2483 pch_udc_ep_set_rrdy(ep);
2495 struct pch_udc_ep *ep = &dev->ep[UDC_EPIN_IDX(ep_num)];
2496 if (list_empty(&ep->queue))
2498 pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
2499 pch_udc_ep_clear_nak(ep);
2510 struct pch_udc_ep *ep;
2515 ep = &dev->ep[UDC_EPIN_IDX(i)];
2516 ep->epsts = pch_udc_read_ep_status(ep);
2517 pch_udc_clear_ep_status(ep, ep->epsts);
2521 ep = &dev->ep[UDC_EPOUT_IDX(i)];
2522 ep->epsts = pch_udc_read_ep_status(ep);
2523 pch_udc_clear_ep_status(ep, ep->epsts);
2535 struct pch_udc_ep *ep;
2539 ep = &dev->ep[UDC_EP0IN_IDX];
2540 pch_udc_clear_ep_control(ep);
2541 pch_udc_ep_fifo_flush(ep, ep->in);
2542 pch_udc_ep_set_bufsz(ep, UDC_EP0IN_BUFF_SIZE, ep->in);
2543 pch_udc_ep_set_maxpkt(ep, UDC_EP0IN_MAX_PKT_SIZE);
2545 ep->td_data = NULL;
2546 ep->td_stp = NULL;
2547 ep->td_data_phys = 0;
2548 ep->td_stp_phys = 0;
2551 ep = &dev->ep[UDC_EP0OUT_IDX];
2552 pch_udc_clear_ep_control(ep);
2553 pch_udc_ep_fifo_flush(ep, ep->in);
2554 pch_udc_ep_set_bufsz(ep, UDC_EP0OUT_BUFF_SIZE, ep->in);
2555 pch_udc_ep_set_maxpkt(ep, UDC_EP0OUT_MAX_PKT_SIZE);
2557 pch_udc_write_csr(ep->dev, val, UDC_EP0OUT_IDX);
2560 pch_udc_init_setup_buff(ep->td_stp);
2562 pch_udc_ep_set_subptr(ep, ep->td_stp_phys);
2564 pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2567 ep->td_data->status = PCH_UDC_DMA_LAST;
2568 ep->td_data->dataptr = dev->dma_addr;
2569 ep->td_data->next = ep->td_data_phys;
2571 pch_udc_ep_clear_nak(ep);
2581 struct pch_udc_ep *ep;
2592 ep = &dev->ep[i];
2593 pch_udc_clear_ep_status(ep, UDC_EPSTS_ALL_CLR_MASK);
2594 pch_udc_clear_ep_control(ep);
2595 pch_udc_ep_set_ddptr(ep, 0);
2596 pch_udc_write_csr(ep->dev, 0x00, i);
2603 /* disable ep to empty req queue. Skip the control EP's */
2605 ep = &dev->ep[i];
2606 pch_udc_ep_set_nak(ep);
2607 pch_udc_ep_fifo_flush(ep, ep->in);
2609 empty_req_queue(ep);
2649 pch_udc_ep_set_rrdy(&(dev->ep[UDC_EP0OUT_IDX]));
2689 pch_udc_ep_clear_stall(&(dev->ep[i]));
2690 dev->ep[i].halted = 0;
2722 pch_udc_ep_clear_stall(&(dev->ep[i]));
2723 dev->ep[i].halted = 0;
2819 /* Clear ep interrupts */
2889 memset(dev->ep, 0, sizeof dev->ep);
2891 struct pch_udc_ep *ep = &dev->ep[i];
2892 ep->dev = dev;
2893 ep->halted = 1;
2894 ep->num = i / 2;
2895 ep->in = ~i & 1;
2896 ep->ep.name = ep_string[i];
2897 ep->ep.ops = &pch_udc_ep_ops;
2898 if (ep->in) {
2899 ep->offset_addr = ep->num * UDC_EP_REG_SHIFT;
2900 ep->ep.caps.dir_in = true;
2902 ep->offset_addr = (UDC_EPINT_OUT_SHIFT + ep->num) *
2904 ep->ep.caps.dir_out = true;
2907 ep->ep.caps.type_control = true;
2909 ep->ep.caps.type_iso = true;
2910 ep->ep.caps.type_bulk = true;
2911 ep->ep.caps.type_int = true;
2913 /* need to set ep->ep.maxpacket and set Default Configuration?*/
2914 usb_ep_set_maxpacket_limit(&ep->ep, UDC_BULK_MAX_PKT_SIZE);
2915 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
2916 INIT_LIST_HEAD(&ep->queue);
2918 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0IN_IDX].ep, UDC_EP0IN_MAX_PKT_SIZE);
2919 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0OUT_IDX].ep, UDC_EP0OUT_MAX_PKT_SIZE);
2922 list_del_init(&dev->ep[UDC_EP0IN_IDX].ep.ep_list);
2923 list_del_init(&dev->ep[UDC_EP0OUT_IDX].ep.ep_list);
2925 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2979 &dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
2985 dev->ep[UDC_EP0OUT_IDX].td_stp = td_stp;
2989 &dev->ep[UDC_EP0OUT_IDX].td_data_phys);
2995 dev->ep[UDC_EP0OUT_IDX].td_data = td_data;
2996 dev->ep[UDC_EP0IN_IDX].td_stp = NULL;
2997 dev->ep[UDC_EP0IN_IDX].td_stp_phys = 0;
2998 dev->ep[UDC_EP0IN_IDX].td_data = NULL;
2999 dev->ep[UDC_EP0IN_IDX].td_data_phys = 0;
3072 if (dev->ep[UDC_EP0OUT_IDX].td_stp) {
3074 dev->ep[UDC_EP0OUT_IDX].td_stp,
3075 dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
3077 if (dev->ep[UDC_EP0OUT_IDX].td_data) {
3079 dev->ep[UDC_EP0OUT_IDX].td_data,
3080 dev->ep[UDC_EP0OUT_IDX].td_data_phys);