Lines Matching refs:x0000
20 #define M66592_XTAL12 0x0000 /* 12MHz */
39 #define M66592_SE0 0x0000 /* SE0 */
58 #define M66592_H_TST_NORMAL 0x0000 /* HOST Normal Mode */
63 #define M66592_P_TST_NORMAL 0x0000 /* PERI Normal Mode */
80 #define M66592_CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
102 #define M66592_MBW_8 0x0000 /* 8bit */
192 #define M66592_SOF_DISABLE 0x0000 /* SOF OUT Disable */
213 #define M66592_DS_POWR 0x0000 /* Powered */
223 #define M66592_CS_IDST 0x0000 /* Idle or setup stage */
250 #define M66592_GET_STATUS 0x0000
265 #define M66592_HOST_TO_DEVICE 0x0000
268 #define M66592_STANDARD 0x0000
272 #define M66592_DEVICE 0x0000
279 #define M66592_ENDPOINT_HALT 0x0000
310 #define M66592_EP_DIR_OUT 0x0000
321 #define M66592_DEVICE_0 0x0000 /* Device address 0 */
337 #define M66592_PID_NAK 0x0000 /* NAK */
341 #define M66592_PIPE0 0x0000 /* PIPE 0 */
362 #define M66592_DIR_H_IN 0x0000 /* HOST IN */
363 #define M66592_DIR_P_OUT 0x0000 /* PERI OUT */