Lines Matching refs:reg
43 u32 reg;
45 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
46 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
54 reg |= mode << 1;
60 dwc3_gadget_dctl_write_safe(dwc, reg);
74 u32 reg;
76 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
78 return DWC3_DSTS_USBLNKST(reg);
92 u32 reg;
100 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
101 if (reg & DWC3_DSTS_DCNRD)
111 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
112 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
115 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
118 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
119 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
131 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
133 if (DWC3_DSTS_USBLNKST(reg) == state)
237 u32 reg;
243 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
244 if (!(reg & DWC3_DGCMD_CMDACT)) {
245 status = DWC3_DGCMD_STATUS(reg);
280 u32 reg;
297 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
298 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
300 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
303 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
305 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
309 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
363 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
364 if (!(reg & DWC3_DEPCMD_CMDACT)) {
365 cmd_status = DWC3_DEPCMD_STATUS(reg);
414 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
415 reg |= saved_config;
416 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
660 u32 reg;
680 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
681 reg |= DWC3_DALEPENA_EP(dep->number);
682 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
796 u32 reg;
804 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
805 reg &= ~DWC3_DALEPENA_EP(dep->number);
806 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
1438 u32 reg;
1440 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1441 return DWC3_DSTS_SOFFN(reg);
2001 u32 reg;
2011 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2013 link_state = DWC3_DSTS_USBLNKST(reg);
2036 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2037 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
2038 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2045 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2048 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
2052 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
2103 u32 reg;
2109 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2112 reg &= ~DWC3_DCTL_TRGTULST_MASK;
2113 reg |= DWC3_DCTL_TRGTULST_RX_DET;
2117 reg &= ~DWC3_DCTL_KEEP_CONNECT;
2118 reg |= DWC3_DCTL_RUN_STOP;
2121 reg |= DWC3_DCTL_KEEP_CONNECT;
2125 reg &= ~DWC3_DCTL_RUN_STOP;
2128 reg &= ~DWC3_DCTL_KEEP_CONNECT;
2133 dwc3_gadget_dctl_write_safe(dwc, reg);
2136 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2137 reg &= DWC3_DSTS_DEVCTRLHLT;
2138 } while (--timeout && !(!is_on ^ !reg));
2251 u32 reg;
2254 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
2264 reg |= DWC3_DEVTEN_ULSTCNGEN;
2268 reg |= DWC3_DEVTEN_EOPFEN;
2270 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2308 u32 reg;
2319 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2320 reg &= ~DWC3_DCFG_NUMP_MASK;
2321 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
2322 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2329 u32 reg;
2349 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
2351 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
2353 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
2355 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
2497 u32 reg;
2500 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2501 reg &= ~(DWC3_DCFG_SPEED_MASK);
2518 reg |= DWC3_DCFG_SUPERSPEED;
2522 reg |= DWC3_DCFG_LOWSPEED;
2525 reg |= DWC3_DCFG_FULLSPEED;
2528 reg |= DWC3_DCFG_HIGHSPEED;
2531 reg |= DWC3_DCFG_SUPERSPEED;
2535 reg |= DWC3_DCFG_SUPERSPEED;
2537 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2543 reg |= DWC3_DCFG_SUPERSPEED;
2545 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2548 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3011 u32 reg;
3024 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3025 reg |= dwc->u1u2;
3026 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3343 int reg;
3347 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3348 reg &= ~DWC3_DCTL_INITU1ENA;
3349 reg &= ~DWC3_DCTL_INITU2ENA;
3350 dwc3_gadget_dctl_write_safe(dwc, reg);
3363 u32 reg;
3415 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3416 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
3417 dwc3_gadget_dctl_write_safe(dwc, reg);
3422 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3423 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
3424 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3431 u32 reg;
3434 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
3435 speed = reg & DWC3_DSTS_CONNECTSPD;
3499 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3500 reg |= DWC3_DCFG_LPM_CAP;
3501 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3503 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3504 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
3506 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold |
3519 reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold);
3521 dwc3_gadget_dctl_write_safe(dwc, reg);
3524 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3525 reg &= ~DWC3_DCFG_LPM_CAP;
3526 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3529 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3530 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
3531 dwc3_gadget_dctl_write_safe(dwc, reg);
3624 u32 reg;
3629 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3630 u1u2 = reg & (DWC3_DCTL_INITU2ENA
3636 dwc->u1u2 = reg & u1u2;
3638 reg &= ~u1u2;
3640 dwc3_gadget_dctl_write_safe(dwc, reg);
3770 u32 reg;
3801 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3802 reg &= ~DWC3_GEVNTSIZ_INTMASK;
3803 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3837 u32 reg;
3869 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3870 reg |= DWC3_GEVNTSIZ_INTMASK;
3871 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);