Lines Matching refs:hsotg
42 static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg)
44 struct dwc2_core_params *p = &hsotg->params;
52 static void dwc2_set_his_params(struct dwc2_hsotg *hsotg)
54 struct dwc2_core_params *p = &hsotg->params;
74 static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg)
76 struct dwc2_core_params *p = &hsotg->params;
82 static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
84 struct dwc2_core_params *p = &hsotg->params;
95 static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)
97 struct dwc2_core_params *p = &hsotg->params;
109 static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)
111 struct dwc2_core_params *p = &hsotg->params;
125 static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg)
127 struct dwc2_core_params *p = &hsotg->params;
135 static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg)
137 struct dwc2_core_params *p = &hsotg->params;
142 static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg)
144 struct dwc2_core_params *p = &hsotg->params;
157 static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg)
159 struct dwc2_core_params *p = &hsotg->params;
166 static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg)
168 struct dwc2_core_params *p = &hsotg->params;
183 static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg)
185 struct dwc2_core_params *p = &hsotg->params;
188 p->activate_stm_id_vb_detection = !device_property_read_bool(hsotg->dev, "usb-role-switch");
202 { .compatible = "samsung,s3c6400-hsotg",
216 { .compatible = "st,stm32f4x9-hsotg" },
217 { .compatible = "st,stm32f7-hsotg",
221 { .compatible = "st,stm32mp15-hsotg",
227 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg)
231 switch (hsotg->hw_params.op_mode) {
245 hsotg->params.otg_cap = val;
248 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg)
251 u32 hs_phy_type = hsotg->hw_params.hs_phy_type;
262 if (dwc2_is_fs_iot(hsotg))
263 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS;
265 hsotg->params.phy_type = val;
268 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg)
272 val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ?
275 if (dwc2_is_fs_iot(hsotg))
278 if (dwc2_is_hs_iot(hsotg))
281 hsotg->params.speed = val;
284 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
288 val = (hsotg->hw_params.utmi_phy_data_width ==
291 if (hsotg->phy) {
296 if (phy_get_bus_width(hsotg->phy) == 8)
300 hsotg->params.phy_utmi_width = val;
303 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
305 struct dwc2_core_params *p = &hsotg->params;
310 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
313 depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg);
318 static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg)
322 if (hsotg->hw_params.hibernation)
324 else if (hsotg->hw_params.power_optimized)
329 hsotg->params.power_down = val;
332 static void dwc2_set_param_lpm(struct dwc2_hsotg *hsotg)
334 struct dwc2_core_params *p = &hsotg->params;
336 p->lpm = hsotg->hw_params.lpm_mode;
353 * @hsotg: Programming view of the DWC_otg controller
356 static void dwc2_set_default_params(struct dwc2_hsotg *hsotg)
358 struct dwc2_hw_params *hw = &hsotg->hw_params;
359 struct dwc2_core_params *p = &hsotg->params;
362 dwc2_set_param_otg_cap(hsotg);
363 dwc2_set_param_phy_type(hsotg);
364 dwc2_set_param_speed(hsotg);
365 dwc2_set_param_phy_utmi_width(hsotg);
366 dwc2_set_param_power_down(hsotg);
367 dwc2_set_param_lpm(hsotg);
388 if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
389 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
401 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
402 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
417 dwc2_set_param_tx_fifo_sizes(hsotg);
424 * @hsotg: Programming view of the DWC_otg controller
428 static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg)
430 struct dwc2_core_params *p = &hsotg->params;
433 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
434 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
435 device_property_read_u32(hsotg->dev, "g-rx-fifo-size",
438 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size",
441 num = device_property_count_u32(hsotg->dev, "g-tx-fifo-size");
446 device_property_read_u32_array(hsotg->dev,
453 if (of_find_property(hsotg->dev->of_node, "disable-over-current", NULL))
457 static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg)
461 switch (hsotg->params.otg_cap) {
463 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
467 switch (hsotg->hw_params.op_mode) {
487 dwc2_set_param_otg_cap(hsotg);
490 static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg)
496 hs_phy_type = hsotg->hw_params.hs_phy_type;
497 fs_phy_type = hsotg->hw_params.fs_phy_type;
499 switch (hsotg->params.phy_type) {
519 dwc2_set_param_phy_type(hsotg);
522 static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg)
525 int phy_type = hsotg->params.phy_type;
526 int speed = hsotg->params.speed;
530 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) &&
543 dwc2_set_param_speed(hsotg);
546 static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
549 int param = hsotg->params.phy_utmi_width;
550 int width = hsotg->hw_params.utmi_phy_data_width;
565 dwc2_set_param_phy_utmi_width(hsotg);
568 static void dwc2_check_param_power_down(struct dwc2_hsotg *hsotg)
570 int param = hsotg->params.power_down;
576 if (hsotg->hw_params.power_optimized)
578 dev_dbg(hsotg->dev,
583 if (hsotg->hw_params.hibernation)
585 dev_dbg(hsotg->dev,
590 dev_err(hsotg->dev,
597 hsotg->params.power_down = param;
600 static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
608 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
609 min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4;
612 total += hsotg->params.g_tx_fifo_size[fifo];
614 if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) {
615 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n",
617 dwc2_set_param_tx_fifo_sizes(hsotg);
621 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo];
623 if (hsotg->params.g_tx_fifo_size[fifo] < min ||
624 hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) {
625 dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n",
627 hsotg->params.g_tx_fifo_size[fifo]);
628 hsotg->params.g_tx_fifo_size[fifo] = dptxfszn;
634 if ((int)(hsotg->params._param) < (_min) || \
635 (hsotg->params._param) > (_max)) { \
636 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
637 __func__, #_param, hsotg->params._param); \
638 hsotg->params._param = (_def); \
643 if (hsotg->params._param && !(_check)) { \
644 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
645 __func__, #_param, hsotg->params._param); \
646 hsotg->params._param = false; \
650 static void dwc2_check_params(struct dwc2_hsotg *hsotg)
652 struct dwc2_hw_params *hw = &hsotg->hw_params;
653 struct dwc2_core_params *p = &hsotg->params;
656 dwc2_check_param_otg_cap(hsotg);
657 dwc2_check_param_phy_type(hsotg);
658 dwc2_check_param_speed(hsotg);
659 dwc2_check_param_phy_utmi_width(hsotg);
660 dwc2_check_param_power_down(hsotg);
666 CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a));
667 CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a));
669 CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm);
670 CHECK_BOOL(besl, hsotg->params.lpm);
671 CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a));
672 CHECK_BOOL(hird_threshold_en, hsotg->params.lpm);
673 CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0);
682 if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
683 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
703 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
704 (hsotg->dr_mode == USB_DR_MODE_OTG)) {
713 dwc2_check_param_tx_fifo_sizes(hsotg);
722 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
724 struct dwc2_hw_params *hw = &hsotg->hw_params;
728 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
731 dwc2_force_mode(hsotg, true);
733 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
734 hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
747 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
749 struct dwc2_hw_params *hw = &hsotg->hw_params;
753 if (hsotg->dr_mode == USB_DR_MODE_HOST)
756 dwc2_force_mode(hsotg, false);
758 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
760 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
764 (dwc2_readl(hsotg, DPTXFSIZN(fifo)) &
776 * @hsotg: Programming view of the DWC_otg controller
779 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
781 struct dwc2_hw_params *hw = &hsotg->hw_params;
786 hwcfg1 = dwc2_readl(hsotg, GHWCFG1);
787 hwcfg2 = dwc2_readl(hsotg, GHWCFG2);
788 hwcfg3 = dwc2_readl(hsotg, GHWCFG3);
789 hwcfg4 = dwc2_readl(hsotg, GHWCFG4);
790 grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
855 dwc2_get_host_hwparams(hsotg);
856 dwc2_get_dev_hwparams(hsotg);
861 int dwc2_init_params(struct dwc2_hsotg *hsotg)
866 dwc2_set_default_params(hsotg);
867 dwc2_get_device_properties(hsotg);
869 match = of_match_device(dwc2_of_match_table, hsotg->dev);
872 set_params(hsotg);
875 dwc2_check_params(hsotg);