Lines Matching refs:hsotg
68 * @hsotg: The HCD state structure for the DWC OTG controller
72 static int dwc2_periodic_channel_available(struct dwc2_hsotg *hsotg)
82 num_channels = hsotg->params.host_channels;
83 if ((hsotg->periodic_channels + hsotg->non_periodic_channels <
84 num_channels) && (hsotg->periodic_channels < num_channels - 1)) {
87 dev_dbg(hsotg->dev,
90 hsotg->periodic_channels, hsotg->non_periodic_channels);
101 * @hsotg: The HCD state structure for the DWC OTG controller
109 static int dwc2_check_periodic_bandwidth(struct dwc2_hsotg *hsotg,
131 if (hsotg->periodic_usecs > max_claimed_usecs) {
132 dev_err(hsotg->dev,
134 __func__, hsotg->periodic_usecs, qh->host_us);
364 * @hsotg: The HCD state structure for the DWC OTG controller.
370 * add logic here to get a map out of "hsotg" if !qh->do_split.
374 static unsigned long *dwc2_get_ls_map(struct dwc2_hsotg *hsotg,
492 struct dwc2_hsotg *hsotg;
506 dwc2_sch_dbg(print_data->hsotg, "QH=%p ...%s\n", print_data->qh, str);
512 * @hsotg: The HCD state structure for the DWC OTG controller.
515 static void dwc2_qh_schedule_print(struct dwc2_hsotg *hsotg,
518 struct dwc2_qh_print_data print_data = { hsotg, qh };
528 unsigned long *map = dwc2_get_ls_map(hsotg, qh);
530 dwc2_sch_dbg(hsotg, "QH=%p LS/FS trans: %d=>%d us @ %d us",
536 dwc2_sch_dbg(hsotg,
552 dwc2_sch_dbg(hsotg,
557 dwc2_sch_dbg(hsotg, "QH=%p Whole high speed map now:\n", qh);
558 pmap_print(hsotg->hs_periodic_bitmap,
565 static inline void dwc2_qh_schedule_print(struct dwc2_hsotg *hsotg,
572 * @hsotg: The HCD state structure for the DWC OTG controller.
584 static int dwc2_ls_pmap_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
588 unsigned long *map = dwc2_get_ls_map(hsotg, qh);
620 * @hsotg: The HCD state structure for the DWC OTG controller.
623 static void dwc2_ls_pmap_unschedule(struct dwc2_hsotg *hsotg,
627 unsigned long *map = dwc2_get_ls_map(hsotg, qh);
647 * @hsotg: The HCD state structure for the DWC OTG controller.
658 static int dwc2_hs_pmap_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
664 us = pmap_schedule(hsotg->hs_periodic_bitmap,
680 * @hsotg: The HCD state structure for the DWC OTG controller.
684 static void dwc2_hs_pmap_unschedule(struct dwc2_hsotg *hsotg,
689 pmap_unschedule(hsotg->hs_periodic_bitmap,
705 * @hsotg: The HCD state structure for the DWC OTG controller.
708 static int dwc2_uframe_schedule_split(struct dwc2_hsotg *hsotg,
749 err = dwc2_ls_pmap_schedule(hsotg, qh, ls_search_slice);
784 dwc2_ls_pmap_unschedule(hsotg, qh);
857 dwc2_sch_dbg(hsotg,
861 dwc2_ls_pmap_unschedule(hsotg, qh);
956 err = dwc2_hs_pmap_schedule(hsotg, qh, true, i);
966 dwc2_hs_pmap_unschedule(hsotg, qh, i);
969 dwc2_ls_pmap_unschedule(hsotg, qh);
987 * @hsotg: The HCD state structure for the DWC OTG controller.
990 static int dwc2_uframe_schedule_hs(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1001 return dwc2_hs_pmap_schedule(hsotg, qh, false, 0);
1010 * @hsotg: The HCD state structure for the DWC OTG controller.
1013 static int dwc2_uframe_schedule_ls(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1021 return dwc2_ls_pmap_schedule(hsotg, qh, 0);
1030 * @hsotg: The HCD state structure for the DWC OTG controller.
1033 static int dwc2_uframe_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1038 ret = dwc2_uframe_schedule_hs(hsotg, qh);
1040 ret = dwc2_uframe_schedule_ls(hsotg, qh);
1042 ret = dwc2_uframe_schedule_split(hsotg, qh);
1045 dwc2_sch_dbg(hsotg, "QH=%p Failed to schedule %d\n", qh, ret);
1047 dwc2_qh_schedule_print(hsotg, qh);
1055 * @hsotg: The HCD state structure for the DWC OTG controller.
1058 static void dwc2_uframe_unschedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1063 dwc2_hs_pmap_unschedule(hsotg, qh, i);
1066 dwc2_ls_pmap_unschedule(hsotg, qh);
1068 dwc2_sch_dbg(hsotg, "QH=%p Unscheduled\n", qh);
1082 * @hsotg: The HCD state structure for the DWC OTG controller
1086 static void dwc2_pick_first_frame(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1098 frame_number = dwc2_hcd_get_frame_number(hsotg);
1112 if (!hsotg->params.uframe_sched) {
1186 dwc2_sch_vdbg(hsotg, "QH=%p First fn=%04x nxt=%04x\n",
1196 * @hsotg: The HCD state structure for the DWC OTG controller
1201 static int dwc2_do_reserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1205 if (hsotg->params.uframe_sched) {
1206 status = dwc2_uframe_schedule(hsotg, qh);
1208 status = dwc2_periodic_channel_available(hsotg);
1210 dev_info(hsotg->dev,
1216 status = dwc2_check_periodic_bandwidth(hsotg, qh);
1220 dev_dbg(hsotg->dev,
1226 if (!hsotg->params.uframe_sched)
1228 hsotg->periodic_channels++;
1231 hsotg->periodic_usecs += qh->host_us;
1233 dwc2_pick_first_frame(hsotg, qh);
1244 * @hsotg: The HCD state structure for the DWC OTG controller
1247 static void dwc2_do_unreserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1249 assert_spin_locked(&hsotg->lock);
1260 hsotg->periodic_usecs -= qh->host_us;
1262 if (hsotg->params.uframe_sched) {
1263 dwc2_uframe_unschedule(hsotg, qh);
1266 hsotg->periodic_channels--;
1285 struct dwc2_hsotg *hsotg = qh->hsotg;
1297 while (!spin_trylock_irqsave(&hsotg->lock, flags)) {
1313 dwc2_do_unreserve(hsotg, qh);
1315 spin_unlock_irqrestore(&hsotg->lock, flags);
1323 * @hsotg: The HCD state structure for the DWC OTG controller
1328 static int dwc2_check_max_xfer_size(struct dwc2_hsotg *hsotg,
1336 max_channel_xfer_size = hsotg->params.max_transfer_size;
1339 dev_err(hsotg->dev,
1352 * @hsotg: The HCD state structure for the DWC OTG controller
1358 static int dwc2_schedule_periodic(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1362 status = dwc2_check_max_xfer_size(hsotg, qh);
1364 dev_dbg(hsotg->dev,
1382 status = dwc2_do_reserve(hsotg, qh);
1393 hsotg->frame_number))
1394 dwc2_pick_first_frame(hsotg, qh);
1399 if (hsotg->params.dma_desc_enable)
1401 list_add_tail(&qh->qh_list_entry, &hsotg->periodic_sched_ready);
1405 &hsotg->periodic_sched_inactive);
1414 * @hsotg: The HCD state structure for the DWC OTG controller
1417 static void dwc2_deschedule_periodic(struct dwc2_hsotg *hsotg,
1422 assert_spin_locked(&hsotg->lock);
1473 struct dwc2_hsotg *hsotg = qh->hsotg;
1476 spin_lock_irqsave(&hsotg->lock, flags);
1488 &hsotg->non_periodic_sched_inactive);
1490 tr_type = dwc2_hcd_select_transactions(hsotg);
1492 dwc2_hcd_queue_transactions(hsotg, tr_type);
1495 spin_unlock_irqrestore(&hsotg->lock, flags);
1502 * @hsotg: The HCD state structure for the DWC OTG controller
1508 static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
1511 int dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
1516 u32 hprt = dwc2_readl(hsotg, HPRT0);
1526 qh->hsotg = hsotg;
1545 struct dwc2_tt *dwc_tt = dwc2_host_get_tt_info(hsotg, urb->priv,
1617 dwc2_sch_dbg(hsotg, "QH=%p Init %s, %s speed, %d bytes:\n", qh, type,
1619 dwc2_sch_dbg(hsotg, "QH=%p ...addr=%d, ep=%d, %s\n", qh,
1624 dwc2_sch_dbg(hsotg,
1627 dwc2_sch_dbg(hsotg, "QH=%p ...interval: host=%d, device=%d\n",
1630 dwc2_sch_dbg(hsotg, "QH=%p ...low speed schedule=%p\n",
1631 qh, dwc2_get_ls_map(hsotg, qh));
1638 * @hsotg: The HCD state structure for the DWC OTG controller
1645 struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
1659 dwc2_qh_init(hsotg, qh, urb, mem_flags);
1661 if (hsotg->params.dma_desc_enable &&
1662 dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) {
1663 dwc2_hcd_qh_free(hsotg, qh);
1673 * @hsotg: HCD instance
1681 void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1687 spin_lock_irqsave(&hsotg->lock, flags);
1688 dwc2_do_unreserve(hsotg, qh);
1689 spin_unlock_irqrestore(&hsotg->lock, flags);
1701 dwc2_host_put_tt_info(hsotg, qh->dwc_tt);
1704 dwc2_hcd_qh_free_ddma(hsotg, qh);
1705 else if (hsotg->unaligned_cache && qh->dw_align_buf)
1706 kmem_cache_free(hsotg->unaligned_cache, qh->dw_align_buf);
1716 * @hsotg: The HCD state structure for the DWC OTG controller
1721 int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1728 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1737 qh->start_active_frame = hsotg->frame_number;
1742 &hsotg->non_periodic_sched_waiting);
1748 &hsotg->non_periodic_sched_inactive);
1753 status = dwc2_schedule_periodic(hsotg, qh);
1756 if (!hsotg->periodic_qh_count) {
1757 intr_mask = dwc2_readl(hsotg, GINTMSK);
1759 dwc2_writel(hsotg, intr_mask, GINTMSK);
1761 hsotg->periodic_qh_count++;
1770 * @hsotg: The HCD state structure
1773 void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1777 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1787 if (hsotg->non_periodic_qh_ptr == &qh->qh_list_entry)
1788 hsotg->non_periodic_qh_ptr =
1789 hsotg->non_periodic_qh_ptr->next;
1794 dwc2_deschedule_periodic(hsotg, qh);
1795 hsotg->periodic_qh_count--;
1796 if (!hsotg->periodic_qh_count &&
1797 !hsotg->params.dma_desc_enable) {
1798 intr_mask = dwc2_readl(hsotg, GINTMSK);
1800 dwc2_writel(hsotg, intr_mask, GINTMSK);
1817 * @hsotg: The HCD state structure
1823 static int dwc2_next_for_periodic_split(struct dwc2_hsotg *hsotg,
1880 * @hsotg: The HCD state structure
1886 static int dwc2_next_periodic_start(struct dwc2_hsotg *hsotg,
1977 void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
1985 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1988 dwc2_hcd_qh_unlink(hsotg, qh);
1991 dwc2_hcd_qh_add(hsotg, qh);
2001 frame_number = dwc2_hcd_get_frame_number(hsotg);
2004 missed = dwc2_next_for_periodic_split(hsotg, qh, frame_number);
2006 missed = dwc2_next_periodic_start(hsotg, qh, frame_number);
2008 dwc2_sch_vdbg(hsotg,
2016 dwc2_hcd_qh_unlink(hsotg, qh);
2024 * Note: we purposely use the frame_number from the "hsotg" structure
2027 if (dwc2_frame_num_le(qh->next_active_frame, hsotg->frame_number))
2029 &hsotg->periodic_sched_ready);
2032 &hsotg->periodic_sched_inactive);
2069 * @hsotg: The DWC HCD structure
2078 int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
2084 dev_err(hsotg->dev, "%s: Invalid QH\n", __func__);
2089 retval = dwc2_hcd_qh_add(hsotg, qh);