Lines Matching refs:hsotg
63 static void dwc2_track_missed_sofs(struct dwc2_hsotg *hsotg)
65 u16 curr_frame_number = hsotg->frame_number;
66 u16 expected = dwc2_frame_num_inc(hsotg->last_frame_num, 1);
69 dwc2_sch_vdbg(hsotg, "MISSED SOF %04x != %04x\n",
73 if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
75 hsotg->frame_num_array[hsotg->frame_num_idx] =
77 hsotg->last_frame_num_array[hsotg->frame_num_idx] =
78 hsotg->last_frame_num;
79 hsotg->frame_num_idx++;
81 } else if (!hsotg->dumped_frame_num_array) {
84 dev_info(hsotg->dev, "Frame Last Frame\n");
85 dev_info(hsotg->dev, "----- ----------\n");
87 dev_info(hsotg->dev, "0x%04x 0x%04x\n",
88 hsotg->frame_num_array[i],
89 hsotg->last_frame_num_array[i]);
91 hsotg->dumped_frame_num_array = 1;
94 hsotg->last_frame_num = curr_frame_number;
97 static void dwc2_hc_handle_tt_clear(struct dwc2_hsotg *hsotg,
101 struct usb_device *root_hub = dwc2_hsotg_to_hcd(hsotg)->self.root_hub;
140 static void dwc2_sof_intr(struct dwc2_hsotg *hsotg)
147 dwc2_writel(hsotg, GINTSTS_SOF, GINTSTS);
150 dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n");
153 hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg);
155 dwc2_track_missed_sofs(hsotg);
158 qh_entry = hsotg->periodic_sched_inactive.next;
159 while (qh_entry != &hsotg->periodic_sched_inactive) {
163 hsotg->frame_number)) {
164 dwc2_sch_vdbg(hsotg, "QH=%p ready fn=%04x, nxt=%04x\n",
165 qh, hsotg->frame_number,
173 &hsotg->periodic_sched_ready);
176 tr_type = dwc2_hcd_select_transactions(hsotg);
178 dwc2_hcd_queue_transactions(hsotg, tr_type);
186 static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg)
192 dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n");
194 grxsts = dwc2_readl(hsotg, GRXSTSP);
196 chan = hsotg->hc_ptr_array[chnum];
198 dev_err(hsotg->dev, "Unable to get corresponding channel\n");
208 dev_vdbg(hsotg->dev, " Ch num = %d\n", chnum);
209 dev_vdbg(hsotg->dev, " Count = %d\n", bcnt);
210 dev_vdbg(hsotg->dev, " DPID = %d, chan.dpid = %d\n", dpid,
212 dev_vdbg(hsotg->dev, " PStatus = %d\n", pktsts);
219 dwc2_read_packet(hsotg, chan->xfer_buf, bcnt);
232 dev_err(hsotg->dev,
244 static void dwc2_np_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
246 dev_vdbg(hsotg->dev, "--Non-Periodic TxFIFO Empty Interrupt--\n");
247 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_NON_PERIODIC);
256 static void dwc2_perio_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
259 dev_vdbg(hsotg->dev, "--Periodic TxFIFO Empty Interrupt--\n");
260 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_PERIODIC);
263 static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
266 struct dwc2_core_params *params = &hsotg->params;
274 dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
277 hfir = dwc2_readl(hsotg, HFIR);
279 hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT &
281 dwc2_writel(hsotg, hfir, HFIR);
286 hsotg->flags.b.port_reset_change = 1;
290 usbcfg = dwc2_readl(hsotg, GUSBCFG);
298 dwc2_writel(hsotg, usbcfg, GUSBCFG);
302 hcfg = dwc2_readl(hsotg, HCFG);
309 dev_vdbg(hsotg->dev,
315 dwc2_writel(hsotg, hcfg, HCFG);
320 dev_vdbg(hsotg->dev,
326 dwc2_writel(hsotg, hcfg, HCFG);
334 dwc2_writel(hsotg, usbcfg, GUSBCFG);
341 dwc2_writel(hsotg, *hprt0_modify, HPRT0);
342 queue_delayed_work(hsotg->wq_otg, &hsotg->reset_work,
346 hsotg->flags.b.port_reset_change = 1;
355 static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
360 dev_vdbg(hsotg->dev, "--Port Interrupt--\n");
362 hprt0 = dwc2_readl(hsotg, HPRT0);
377 dwc2_writel(hsotg, hprt0_modify | HPRT0_CONNDET, HPRT0);
379 dev_vdbg(hsotg->dev,
382 dwc2_hcd_connect(hsotg);
395 dwc2_writel(hsotg, hprt0_modify | HPRT0_ENACHG, HPRT0);
396 dev_vdbg(hsotg->dev,
400 hsotg->new_connection = true;
401 dwc2_hprt0_enable(hsotg, hprt0, &hprt0_modify);
403 hsotg->flags.b.port_enable_change = 1;
404 if (hsotg->params.dma_desc_fs_enable) {
407 hsotg->params.dma_desc_enable = false;
408 hsotg->new_connection = false;
409 hcfg = dwc2_readl(hsotg, HCFG);
411 dwc2_writel(hsotg, hcfg, HCFG);
418 dwc2_writel(hsotg, hprt0_modify | HPRT0_OVRCURRCHG,
420 dev_vdbg(hsotg->dev,
423 hsotg->flags.b.port_over_current_change = 1;
436 static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg,
444 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
481 * @hsotg: Programming view of the DWC_otg controller
490 static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg,
498 int xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
503 dev_dbg(hsotg->dev, "%s(): trimming xfer length\n", __func__);
507 dev_vdbg(hsotg->dev, "urb->actual_length=%d xfer_length=%d\n",
521 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
522 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
524 dev_vdbg(hsotg->dev, " chan->xfer_len %d\n", chan->xfer_len);
525 dev_vdbg(hsotg->dev, " hctsiz.xfersize %d\n",
527 dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n", urb->length);
528 dev_vdbg(hsotg->dev, " urb->actual_length %d\n", urb->actual_length);
529 dev_vdbg(hsotg->dev, " short_read %d, xfer_done %d\n", short_read,
540 void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
544 u32 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
575 * @hsotg: Programming view of the DWC_otg controller
585 struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
600 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
619 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
625 hsotg->params.host_dma) {
632 dev_err(hsotg->dev, "Unhandled halt_status (%d)\n",
642 dwc2_host_complete(hsotg, qtd, 0);
658 static void dwc2_deactivate_qh(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
665 dev_vdbg(hsotg->dev, " %s(%p,%p,%d)\n", __func__,
666 hsotg, qh, free_qtd);
669 dev_dbg(hsotg->dev, "## QTD list empty ##\n");
682 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
688 dwc2_hcd_qh_deactivate(hsotg, qh, continue_split);
694 * @hsotg: The HCD state structure
704 static void dwc2_release_channel(struct dwc2_hsotg *hsotg,
714 dev_vdbg(hsotg->dev, " %s: channel %d, halt_status %d\n",
728 dev_vdbg(hsotg->dev,
731 dwc2_host_complete(hsotg, qtd, -EPROTO);
742 dev_vdbg(hsotg->dev, " Complete URB with I/O error\n");
744 dwc2_host_complete(hsotg, qtd, -EIO);
751 dwc2_deactivate_qh(hsotg, chan->qh, free_qtd);
761 dwc2_hc_cleanup(hsotg, chan);
762 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
764 if (hsotg->params.uframe_sched) {
765 hsotg->available_host_channels++;
770 hsotg->non_periodic_channels--;
783 haintmsk = dwc2_readl(hsotg, HAINTMSK);
785 dwc2_writel(hsotg, haintmsk, HAINTMSK);
788 tr_type = dwc2_hcd_select_transactions(hsotg);
790 dwc2_hcd_queue_transactions(hsotg, tr_type);
803 static void dwc2_halt_channel(struct dwc2_hsotg *hsotg,
808 dev_vdbg(hsotg->dev, "%s()\n", __func__);
810 if (hsotg->params.host_dma) {
812 dev_vdbg(hsotg->dev, "DMA enabled\n");
813 dwc2_release_channel(hsotg, chan, qtd, halt_status);
818 dwc2_hc_halt(hsotg, chan, halt_status);
823 dev_vdbg(hsotg->dev, "Halt on queue\n");
826 dev_vdbg(hsotg->dev, "control/bulk\n");
832 gintmsk = dwc2_readl(hsotg, GINTMSK);
834 dwc2_writel(hsotg, gintmsk, GINTMSK);
836 dev_vdbg(hsotg->dev, "isoc/intr\n");
844 &hsotg->periodic_sched_assigned);
851 gintmsk = dwc2_readl(hsotg, GINTMSK);
853 dwc2_writel(hsotg, gintmsk, GINTMSK);
863 static void dwc2_complete_non_periodic_xfer(struct dwc2_hsotg *hsotg,
868 dev_vdbg(hsotg->dev, "%s()\n", __func__);
878 dev_vdbg(hsotg->dev, "got NYET\n");
898 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
904 dwc2_release_channel(hsotg, chan, qtd, halt_status);
913 static void dwc2_complete_periodic_xfer(struct dwc2_hsotg *hsotg,
918 u32 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
924 dwc2_release_channel(hsotg, chan, qtd, halt_status);
927 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
930 static int dwc2_xfercomp_isoc_split_in(struct dwc2_hsotg *hsotg,
943 len = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
953 dev_vdbg(hsotg->dev, "non-aligned buffer\n");
954 dma_unmap_single(hsotg->dev, chan->qh->dw_align_buf_dma,
962 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
973 dwc2_host_complete(hsotg, qtd, 0);
974 dwc2_release_channel(hsotg, chan, qtd,
977 dwc2_release_channel(hsotg, chan, qtd,
988 static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg,
998 dev_vdbg(hsotg->dev,
1007 if (hsotg->params.dma_desc_enable) {
1008 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, halt_status);
1018 hsotg->params.host_dma) {
1020 dwc2_xfercomp_isoc_split_in(hsotg, chan, chnum,
1037 dev_vdbg(hsotg->dev,
1042 urb_xfer_done = dwc2_update_urb_state(hsotg, chan,
1046 dev_vdbg(hsotg->dev,
1049 dwc2_hcd_save_data_toggle(hsotg, chan, chnum,
1055 dev_vdbg(hsotg->dev, " Control transfer complete\n");
1058 dwc2_host_complete(hsotg, qtd, urb->status);
1063 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1067 dev_vdbg(hsotg->dev, " Bulk transfer complete\n");
1068 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1071 dwc2_host_complete(hsotg, qtd, urb->status);
1077 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1078 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1082 dev_vdbg(hsotg->dev, " Interrupt transfer complete\n");
1083 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1091 dwc2_host_complete(hsotg, qtd, urb->status);
1097 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1098 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1103 dev_vdbg(hsotg->dev, " Isochronous transfer complete\n");
1105 halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1108 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1114 disable_hc_int(hsotg, chnum, HCINTMSK_XFERCOMPL);
1121 static void dwc2_hc_stall_intr(struct dwc2_hsotg *hsotg,
1128 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: STALL Received--\n",
1131 if (hsotg->params.dma_desc_enable) {
1132 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1143 dwc2_host_complete(hsotg, qtd, -EPIPE);
1147 dwc2_host_complete(hsotg, qtd, -EPIPE);
1159 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_STALL);
1162 disable_hc_int(hsotg, chnum, HCINTMSK_STALL);
1171 static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg,
1177 u32 xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum,
1182 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
1188 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
1189 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
1191 dev_vdbg(hsotg->dev, " chan->start_pkt_count %d\n",
1193 dev_vdbg(hsotg->dev, " hctsiz.pktcnt %d\n",
1195 dev_vdbg(hsotg->dev, " chan->max_packet %d\n", chan->max_packet);
1196 dev_vdbg(hsotg->dev, " bytes_transferred %d\n",
1198 dev_vdbg(hsotg->dev, " urb->actual_length %d\n",
1200 dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n",
1208 static void dwc2_hc_nak_intr(struct dwc2_hsotg *hsotg,
1213 dev_dbg(hsotg->dev, "%s: qtd is NULL\n", __func__);
1218 dev_dbg(hsotg->dev, "%s: qtd->urb is NULL\n", __func__);
1223 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NAK Received--\n",
1253 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1260 if (hsotg->params.host_dma && chan->ep_is_in) {
1279 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1281 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1292 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1296 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1300 dev_err(hsotg->dev, "NACK interrupt for ISOC transfer\n");
1305 disable_hc_int(hsotg, chnum, HCINTMSK_NAK);
1313 static void dwc2_hc_ack_intr(struct dwc2_hsotg *hsotg,
1320 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: ACK Received--\n",
1331 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1374 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1382 disable_hc_int(hsotg, chnum, HCINTMSK_ACK);
1392 static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg,
1397 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NYET Received--\n",
1406 hsotg->params.host_dma) {
1412 dwc2_host_complete(hsotg, qtd, 0);
1413 dwc2_release_channel(hsotg, chan, qtd,
1416 dwc2_release_channel(hsotg, chan, qtd,
1427 if (!hsotg->params.uframe_sched) {
1428 int frnum = dwc2_hcd_get_frame_number(hsotg);
1484 dwc2_halt_channel(hsotg, chan, qtd,
1491 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1498 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, qtd,
1500 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1506 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1509 disable_hc_int(hsotg, chnum, HCINTMSK_NYET);
1516 static void dwc2_hc_babble_intr(struct dwc2_hsotg *hsotg,
1520 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Babble Error--\n",
1523 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1525 if (hsotg->params.dma_desc_enable) {
1526 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1532 dwc2_host_complete(hsotg, qtd, -EOVERFLOW);
1533 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_BABBLE_ERR);
1537 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1539 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1543 disable_hc_int(hsotg, chnum, HCINTMSK_BBLERR);
1550 static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg,
1561 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: AHB Error--\n",
1567 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1569 hcchar = dwc2_readl(hsotg, HCCHAR(chnum));
1570 hcsplt = dwc2_readl(hsotg, HCSPLT(chnum));
1571 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
1572 hc_dma = dwc2_readl(hsotg, HCDMA(chnum));
1574 dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum);
1575 dev_err(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt);
1576 dev_err(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", hctsiz, hc_dma);
1577 dev_err(hsotg->dev, " Device address: %d\n",
1579 dev_err(hsotg->dev, " Endpoint: %d, %s\n",
1601 dev_err(hsotg->dev, " Endpoint type: %s\n", pipetype);
1618 dev_err(hsotg->dev, " Speed: %s\n", speed);
1620 dev_err(hsotg->dev, " Max packet size: %d (mult %d)\n",
1623 dev_err(hsotg->dev, " Data buffer length: %d\n", urb->length);
1624 dev_err(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
1626 dev_err(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
1628 dev_err(hsotg->dev, " Interval: %d\n", urb->interval);
1631 if (hsotg->params.dma_desc_enable) {
1632 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1637 dwc2_host_complete(hsotg, qtd, -EIO);
1644 dwc2_hc_halt(hsotg, chan, DWC2_HC_XFER_AHB_ERR);
1647 disable_hc_int(hsotg, chnum, HCINTMSK_AHBERR);
1654 static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg,
1658 dev_dbg(hsotg->dev,
1661 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1663 if (hsotg->params.dma_desc_enable) {
1664 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1674 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1676 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1685 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1691 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1697 halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1699 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1705 disable_hc_int(hsotg, chnum, HCINTMSK_XACTERR);
1712 static void dwc2_hc_frmovrun_intr(struct dwc2_hsotg *hsotg,
1719 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Frame Overrun--\n",
1722 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1729 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1732 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1734 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1738 disable_hc_int(hsotg, chnum, HCINTMSK_FRMOVRUN);
1745 static void dwc2_hc_datatglerr_intr(struct dwc2_hsotg *hsotg,
1749 dev_dbg(hsotg->dev,
1755 dev_err(hsotg->dev,
1759 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1760 disable_hc_int(hsotg, chnum, HCINTMSK_DATATGLERR);
1770 static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg,
1785 hcchar = dwc2_readl(hsotg, HCCHAR(chnum));
1786 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum));
1787 hcintmsk = dwc2_readl(hsotg, HCINTMSK(chnum));
1788 hcsplt = dwc2_readl(hsotg, HCSPLT(chnum));
1789 dev_dbg(hsotg->dev,
1792 dev_dbg(hsotg->dev,
1795 dev_dbg(hsotg->dev,
1799 dev_dbg(hsotg->dev, "qtd->complete_split %d\n",
1801 dev_warn(hsotg->dev,
1812 hcchar = dwc2_readl(hsotg, HCCHAR(chnum));
1814 dev_warn(hsotg->dev,
1818 dwc2_halt_channel(hsotg, chan, qtd, chan->halt_status);
1830 static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
1838 dev_vdbg(hsotg->dev,
1846 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_71a) {
1856 !hsotg->params.dma_desc_enable)) {
1857 if (hsotg->params.dma_desc_enable)
1858 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1867 dwc2_release_channel(hsotg, chan, qtd,
1872 hcintmsk = dwc2_readl(hsotg, HCINTMSK(chnum));
1883 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1884 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
1886 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
1888 !hsotg->params.dma_desc_enable) {
1892 dev_vdbg(hsotg->dev,
1896 dev_vdbg(hsotg->dev,
1906 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1908 hsotg->params.dma_desc_enable) {
1909 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1911 hsotg->params.dma_desc_enable) {
1912 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
1914 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
1916 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
1925 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
1935 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
1945 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1955 dev_dbg(hsotg->dev,
1958 dwc2_halt_channel(hsotg, chan, qtd,
1961 dev_err(hsotg->dev,
1964 dev_err(hsotg->dev,
1967 dwc2_readl(hsotg, GINTSTS));
1972 dev_info(hsotg->dev,
1978 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1992 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1993 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
2008 static void dwc2_hc_chhltd_intr(struct dwc2_hsotg *hsotg,
2013 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: Channel Halted--\n",
2016 if (hsotg->params.host_dma) {
2017 dwc2_hc_chhltd_intr_dma(hsotg, chan, chnum, qtd);
2019 if (!dwc2_halt_status_ok(hsotg, chan, chnum, qtd))
2021 dwc2_release_channel(hsotg, chan, qtd, chan->halt_status);
2044 static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum)
2050 chan = hsotg->hc_ptr_array[chnum];
2052 hcintraw = dwc2_readl(hsotg, HCINT(chnum));
2053 hcintmsk = dwc2_readl(hsotg, HCINTMSK(chnum));
2055 dwc2_writel(hsotg, hcint, HCINT(chnum));
2058 dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n");
2063 dev_vdbg(hsotg->dev, "--Host Channel Interrupt--, Channel %d\n",
2065 dev_vdbg(hsotg->dev,
2075 dev_warn(hsotg->dev, "Interrupt on disabled channel\n");
2092 if (hsotg->params.dma_desc_enable)
2093 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
2096 dwc2_release_channel(hsotg, chan, NULL,
2106 dev_dbg(hsotg->dev, "## no QTD queued for channel %d ##\n",
2108 dev_dbg(hsotg->dev,
2112 disable_hc_int(hsotg, chnum, HCINTMSK_CHHLTD);
2120 if (!hsotg->params.host_dma) {
2126 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
2136 dwc2_hc_chhltd_intr(hsotg, chan, chnum, qtd);
2141 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
2146 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
2151 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
2156 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
2161 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
2166 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
2171 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
2176 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
2181 dwc2_hc_datatglerr_intr(hsotg, chan, chnum, qtd);
2196 static void dwc2_hc_intr(struct dwc2_hsotg *hsotg)
2202 haint = dwc2_readl(hsotg, HAINT);
2204 dev_vdbg(hsotg->dev, "%s()\n", __func__);
2206 dev_vdbg(hsotg->dev, "HAINT=%08x\n", haint);
2215 list_for_each_entry_safe(chan, chan_tmp, &hsotg->split_order,
2220 dwc2_hc_n_intr(hsotg, hc_num);
2225 for (i = 0; i < hsotg->params.host_channels; i++) {
2227 dwc2_hc_n_intr(hsotg, i);
2232 irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg)
2237 if (!dwc2_is_controller_alive(hsotg)) {
2238 dev_warn(hsotg->dev, "Controller is dead\n");
2242 spin_lock(&hsotg->lock);
2245 if (dwc2_is_host_mode(hsotg)) {
2246 gintsts = dwc2_read_core_intr(hsotg);
2248 spin_unlock(&hsotg->lock);
2264 dev_vdbg(hsotg->dev,
2269 dwc2_sof_intr(hsotg);
2271 dwc2_rx_fifo_level_intr(hsotg);
2273 dwc2_np_tx_fifo_empty_intr(hsotg);
2275 dwc2_port_intr(hsotg);
2277 dwc2_hc_intr(hsotg);
2279 dwc2_perio_tx_fifo_empty_intr(hsotg);
2282 dev_vdbg(hsotg->dev,
2284 dev_vdbg(hsotg->dev,
2286 dwc2_readl(hsotg, GINTSTS),
2287 dwc2_readl(hsotg, GINTMSK));
2291 spin_unlock(&hsotg->lock);