Lines Matching refs:hsotg
88 static int dwc2_desc_list_alloc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
95 desc_cache = hsotg->desc_hsisoc_cache;
97 desc_cache = hsotg->desc_gen_cache;
106 qh->desc_list_dma = dma_map_single(hsotg->dev, qh->desc_list,
112 dma_unmap_single(hsotg->dev, qh->desc_list_dma,
123 static void dwc2_desc_list_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
129 desc_cache = hsotg->desc_hsisoc_cache;
131 desc_cache = hsotg->desc_gen_cache;
134 dma_unmap_single(hsotg->dev, qh->desc_list_dma,
144 static int dwc2_frame_list_alloc(struct dwc2_hsotg *hsotg, gfp_t mem_flags)
146 if (hsotg->frame_list)
149 hsotg->frame_list_sz = 4 * FRLISTEN_64_SIZE;
150 hsotg->frame_list = kzalloc(hsotg->frame_list_sz, GFP_ATOMIC | GFP_DMA);
151 if (!hsotg->frame_list)
154 hsotg->frame_list_dma = dma_map_single(hsotg->dev, hsotg->frame_list,
155 hsotg->frame_list_sz,
161 static void dwc2_frame_list_free(struct dwc2_hsotg *hsotg)
165 spin_lock_irqsave(&hsotg->lock, flags);
167 if (!hsotg->frame_list) {
168 spin_unlock_irqrestore(&hsotg->lock, flags);
172 dma_unmap_single(hsotg->dev, hsotg->frame_list_dma,
173 hsotg->frame_list_sz, DMA_FROM_DEVICE);
175 kfree(hsotg->frame_list);
176 hsotg->frame_list = NULL;
178 spin_unlock_irqrestore(&hsotg->lock, flags);
181 static void dwc2_per_sched_enable(struct dwc2_hsotg *hsotg, u32 fr_list_en)
186 spin_lock_irqsave(&hsotg->lock, flags);
188 hcfg = dwc2_readl(hsotg, HCFG);
191 spin_unlock_irqrestore(&hsotg->lock, flags);
195 dwc2_writel(hsotg, hsotg->frame_list_dma, HFLBADDR);
199 dev_vdbg(hsotg->dev, "Enabling Periodic schedule\n");
200 dwc2_writel(hsotg, hcfg, HCFG);
202 spin_unlock_irqrestore(&hsotg->lock, flags);
205 static void dwc2_per_sched_disable(struct dwc2_hsotg *hsotg)
210 spin_lock_irqsave(&hsotg->lock, flags);
212 hcfg = dwc2_readl(hsotg, HCFG);
215 spin_unlock_irqrestore(&hsotg->lock, flags);
220 dev_vdbg(hsotg->dev, "Disabling Periodic schedule\n");
221 dwc2_writel(hsotg, hcfg, HCFG);
223 spin_unlock_irqrestore(&hsotg->lock, flags);
230 static void dwc2_update_frame_list(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
236 if (!hsotg) {
237 pr_err("hsotg = %p\n", hsotg);
242 dev_err(hsotg->dev, "qh->channel = %p\n", qh->channel);
246 if (!hsotg->frame_list) {
247 dev_err(hsotg->dev, "hsotg->frame_list = %p\n",
248 hsotg->frame_list);
262 hsotg->frame_list[j] |= 1 << chan->hc_num;
264 hsotg->frame_list[j] &= ~(1 << chan->hc_num);
272 dma_sync_single_for_device(hsotg->dev,
273 hsotg->frame_list_dma,
274 hsotg->frame_list_sz,
294 static void dwc2_release_channel_ddma(struct dwc2_hsotg *hsotg,
300 if (hsotg->params.uframe_sched)
301 hsotg->available_host_channels++;
303 hsotg->non_periodic_channels--;
305 dwc2_update_frame_list(hsotg, qh, 0);
306 hsotg->available_host_channels++;
316 dwc2_hc_cleanup(hsotg, chan);
317 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
333 * @hsotg: The HCD state structure for the DWC OTG controller
342 int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
348 dev_err(hsotg->dev,
354 retval = dwc2_desc_list_alloc(hsotg, qh, mem_flags);
360 if (!hsotg->frame_list) {
361 retval = dwc2_frame_list_alloc(hsotg, mem_flags);
365 dwc2_per_sched_enable(hsotg, HCFG_FRLISTEN_64);
373 dwc2_desc_list_free(hsotg, qh);
382 * @hsotg: The HCD state structure for the DWC OTG controller
388 void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
392 dwc2_desc_list_free(hsotg, qh);
401 spin_lock_irqsave(&hsotg->lock, flags);
403 dwc2_release_channel_ddma(hsotg, qh);
404 spin_unlock_irqrestore(&hsotg->lock, flags);
408 (hsotg->params.uframe_sched ||
409 !hsotg->periodic_channels) && hsotg->frame_list) {
410 dwc2_per_sched_disable(hsotg);
411 dwc2_frame_list_free(hsotg);
428 static u16 dwc2_calc_starting_frame(struct dwc2_hsotg *hsotg,
433 hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg);
462 if (dwc2_micro_frame_num(hsotg->frame_number) >= 5) {
464 frame = dwc2_frame_num_inc(hsotg->frame_number,
468 frame = dwc2_frame_num_inc(hsotg->frame_number,
480 frame = dwc2_frame_num_inc(hsotg->frame_number, 2);
490 static u16 dwc2_recalc_initial_desc_idx(struct dwc2_hsotg *hsotg,
514 frame = dwc2_calc_starting_frame(hsotg, qh, &skip_frames);
525 qh->next_active_frame = dwc2_calc_starting_frame(hsotg, qh,
541 static void dwc2_fill_host_isoc_dma_desc(struct dwc2_hsotg *hsotg,
573 dma_sync_single_for_device(hsotg->dev,
580 static void dwc2_init_isoc_dma_desc(struct dwc2_hsotg *hsotg,
591 hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg);
592 cur_idx = dwc2_frame_list_idx(hsotg->frame_number);
604 dev_vdbg(hsotg->dev,
631 dwc2_fill_host_isoc_dma_desc(hsotg, qtd, qh,
647 dma_sync_single_for_device(hsotg->dev,
681 dma_sync_single_for_device(hsotg->dev,
689 static void dwc2_fill_host_dma_desc(struct dwc2_hsotg *hsotg,
723 dma_sync_single_for_device(hsotg->dev,
741 static void dwc2_init_non_isoc_dma_desc(struct dwc2_hsotg *hsotg,
748 dev_vdbg(hsotg->dev, "%s(): qh=%p dma=%08lx len=%d\n", __func__, qh,
759 dev_vdbg(hsotg->dev, "qtd=%p\n", qtd);
767 dev_vdbg(hsotg->dev, "buf=%08lx len=%d\n",
775 dev_vdbg(hsotg->dev,
779 dma_sync_single_for_device(hsotg->dev,
786 dwc2_fill_host_dma_desc(hsotg, chan, qtd, qh, n_desc);
787 dev_vdbg(hsotg->dev,
797 dev_vdbg(hsotg->dev, "n_desc=%d\n", n_desc);
808 dev_vdbg(hsotg->dev, "set IOC/EOL/A bits in desc %d (%p)\n",
810 dma_sync_single_for_device(hsotg->dev,
817 dev_vdbg(hsotg->dev, "set A bit in desc 0 (%p)\n",
819 dma_sync_single_for_device(hsotg->dev,
831 * @hsotg: The HCD state structure for the DWC OTG controller
847 void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
856 dwc2_init_non_isoc_dma_desc(hsotg, qh);
857 dwc2_hc_start_transfer_ddma(hsotg, chan);
860 dwc2_init_non_isoc_dma_desc(hsotg, qh);
861 dwc2_update_frame_list(hsotg, qh, 1);
862 dwc2_hc_start_transfer_ddma(hsotg, chan);
866 skip_frames = dwc2_recalc_initial_desc_idx(hsotg, qh);
867 dwc2_init_isoc_dma_desc(hsotg, qh, skip_frames);
870 dwc2_update_frame_list(hsotg, qh, 1);
880 dwc2_hc_start_transfer_ddma(hsotg, chan);
892 static int dwc2_cmpl_host_isoc_dma_desc(struct dwc2_hsotg *hsotg,
905 dma_sync_single_for_cpu(hsotg->dev, qh->desc_list_dma + (idx *
938 dwc2_host_complete(hsotg, qtd, 0);
939 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
961 static void dwc2_complete_isoc_xfer_ddma(struct dwc2_hsotg *hsotg,
1003 dwc2_host_complete(hsotg, qtd, err);
1006 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1022 dev_vdbg(hsotg->dev,
1032 rc = dwc2_cmpl_host_isoc_dma_desc(hsotg, chan, qtd, qh,
1050 cur_idx = dwc2_frame_list_idx(hsotg->frame_number);
1067 static int dwc2_update_non_isoc_urb_state_ddma(struct dwc2_hsotg *hsotg,
1081 dev_vdbg(hsotg->dev, "remain=%d dwc2_urb=%p\n", remain, urb);
1084 dev_err(hsotg->dev, "EIO\n");
1092 dev_vdbg(hsotg->dev, "Stall\n");
1096 dev_err(hsotg->dev, "Babble\n");
1100 dev_err(hsotg->dev, "XactErr\n");
1104 dev_err(hsotg->dev,
1113 dev_vdbg(hsotg->dev,
1138 dev_vdbg(hsotg->dev, "length=%d actual=%d\n", urb->length,
1149 static int dwc2_process_non_isoc_desc(struct dwc2_hsotg *hsotg,
1162 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1167 dma_sync_single_for_cpu(hsotg->dev,
1175 dev_vdbg(hsotg->dev,
1178 failed = dwc2_update_non_isoc_urb_state_ddma(hsotg, chan, qtd, dma_desc,
1182 dwc2_host_complete(hsotg, qtd, urb->status);
1183 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1184 dev_vdbg(hsotg->dev, "failed=%1x xfer_done=%1x\n",
1196 dev_vdbg(hsotg->dev,
1202 dev_vdbg(hsotg->dev,
1209 dwc2_hcd_save_data_toggle(hsotg, chan, chnum,
1221 static void dwc2_complete_non_isoc_xfer_ddma(struct dwc2_hsotg *hsotg,
1247 if (dwc2_process_non_isoc_desc(hsotg, chan, chnum, qtd,
1267 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, NULL);
1287 * @hsotg: The HCD state structure for the DWC OTG controller
1299 void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg,
1308 dwc2_complete_isoc_xfer_ddma(hsotg, chan, halt_status);
1322 dwc2_host_complete(hsotg, qtd,
1324 dwc2_hcd_qtd_unlink_and_free(hsotg,
1330 dwc2_hc_halt(hsotg, chan, halt_status);
1331 dwc2_release_channel_ddma(hsotg, qh);
1332 dwc2_hcd_qh_unlink(hsotg, qh);
1336 &hsotg->periodic_sched_assigned);
1353 dwc2_complete_non_isoc_xfer_ddma(hsotg, chan, chnum,
1355 dwc2_release_channel_ddma(hsotg, qh);
1356 dwc2_hcd_qh_unlink(hsotg, qh);
1363 dwc2_hcd_qh_add(hsotg, qh);
1367 tr_type = dwc2_hcd_select_transactions(hsotg);
1375 dwc2_hcd_queue_transactions(hsotg, tr_type);