Lines Matching refs:hsotg
59 static void dwc2_port_resume(struct dwc2_hsotg *hsotg);
71 * @hsotg: Programming view of the DWC_otg controller
73 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
78 dwc2_writel(hsotg, 0xffffffff, GOTGINT);
81 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
86 if (!hsotg->params.host_dma)
88 if (!hsotg->params.external_id_pin_ctl)
94 if (dwc2_is_device_mode(hsotg) && hsotg->params.lpm)
97 dwc2_writel(hsotg, intmsk, GINTMSK);
100 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
102 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
104 switch (hsotg->hw_params.arch) {
106 dev_err(hsotg->dev, "External DMA Mode not supported\n");
110 dev_dbg(hsotg->dev, "Internal DMA Mode\n");
111 if (hsotg->params.ahbcfg != -1) {
113 ahbcfg |= hsotg->params.ahbcfg &
120 dev_dbg(hsotg->dev, "Slave Only Mode\n");
124 if (hsotg->params.host_dma)
127 hsotg->params.dma_desc_enable = false;
129 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
134 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
138 usbcfg = dwc2_readl(hsotg, GUSBCFG);
141 switch (hsotg->hw_params.op_mode) {
143 if (hsotg->params.otg_cap ==
146 if (hsotg->params.otg_cap !=
154 if (hsotg->params.otg_cap !=
166 dwc2_writel(hsotg, usbcfg, GUSBCFG);
169 static int dwc2_vbus_supply_init(struct dwc2_hsotg *hsotg)
171 if (hsotg->vbus_supply)
172 return regulator_enable(hsotg->vbus_supply);
177 static int dwc2_vbus_supply_exit(struct dwc2_hsotg *hsotg)
179 if (hsotg->vbus_supply)
180 return regulator_disable(hsotg->vbus_supply);
188 * @hsotg: Programming view of DWC_otg controller
190 static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
194 dev_dbg(hsotg->dev, "%s()\n", __func__);
197 dwc2_writel(hsotg, 0, GINTMSK);
198 dwc2_writel(hsotg, 0, HAINTMSK);
201 dwc2_enable_common_interrupts(hsotg);
204 intmsk = dwc2_readl(hsotg, GINTMSK);
206 dwc2_writel(hsotg, intmsk, GINTMSK);
212 * @hsotg: Programming view of DWC_otg controller
214 static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
216 u32 intmsk = dwc2_readl(hsotg, GINTMSK);
221 dwc2_writel(hsotg, intmsk, GINTMSK);
229 * @hsotg: Programming view of DWC_otg controller
231 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg)
233 struct dwc2_core_params *params = &hsotg->params;
234 struct dwc2_hw_params *hw = &hsotg->hw_params;
287 dev_err(hsotg->dev, "invalid fifo sizes\n");
290 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
292 struct dwc2_core_params *params = &hsotg->params;
298 dwc2_calculate_dynamic_fifo(hsotg);
301 grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
302 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
306 dwc2_writel(hsotg, grxfsiz, GRXFSIZ);
307 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n",
308 dwc2_readl(hsotg, GRXFSIZ));
311 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
312 dwc2_readl(hsotg, GNPTXFSIZ));
317 dwc2_writel(hsotg, nptxfsiz, GNPTXFSIZ);
318 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
319 dwc2_readl(hsotg, GNPTXFSIZ));
322 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
323 dwc2_readl(hsotg, HPTXFSIZ));
329 dwc2_writel(hsotg, hptxfsiz, HPTXFSIZ);
330 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
331 dwc2_readl(hsotg, HPTXFSIZ));
333 if (hsotg->params.en_multiple_tx_fifo &&
334 hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) {
340 dfifocfg = dwc2_readl(hsotg, GDFIFOCFG);
347 dwc2_writel(hsotg, dfifocfg, GDFIFOCFG);
355 * @hsotg: Programming view of DWC_otg controller
361 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
367 usbcfg = dwc2_readl(hsotg, GUSBCFG);
368 hprt0 = dwc2_readl(hsotg, HPRT0);
373 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type ==
386 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)
389 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
404 * @hsotg: Programming view of DWC_otg controller
408 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
420 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
423 *data_buf = dwc2_readl(hsotg, HCFIFO(0));
429 * @hsotg: Programming view of DWC_otg controller
437 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
441 int num_channels = hsotg->params.host_channels;
452 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
453 hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num));
454 hctsiz = dwc2_readl(hsotg, HCTSIZ(chan->hc_num));
455 hc_dma = dwc2_readl(hsotg, HCDMA(chan->hc_num));
457 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan);
458 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n",
460 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n",
462 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
464 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
465 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
466 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start);
467 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started);
468 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
469 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
470 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
472 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
473 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
474 dev_dbg(hsotg->dev, " NP inactive sched:\n");
475 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
477 dev_dbg(hsotg->dev, " %p\n", qh);
478 dev_dbg(hsotg->dev, " NP waiting sched:\n");
479 list_for_each_entry(qh, &hsotg->non_periodic_sched_waiting,
481 dev_dbg(hsotg->dev, " %p\n", qh);
482 dev_dbg(hsotg->dev, " NP active sched:\n");
483 list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
485 dev_dbg(hsotg->dev, " %p\n", qh);
486 dev_dbg(hsotg->dev, " Channels:\n");
488 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
490 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan);
497 static void dwc2_host_start(struct dwc2_hsotg *hsotg)
499 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
501 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
505 static void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
507 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
512 static void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context,
530 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg,
538 dev_vdbg(hsotg->dev, "control/bulk\n");
566 dev_vdbg(hsotg->dev, "intr\n");
588 dev_vdbg(hsotg->dev, "isoc\n");
599 dev_err(hsotg->dev, "## Unknown EP type ##\n");
603 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
605 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
608 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
617 if (!hsotg->params.dma_desc_enable) {
619 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
623 dev_vdbg(hsotg->dev, "desc DMA enabled\n");
631 dev_vdbg(hsotg->dev, "setting ACK\n");
640 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
642 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
645 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
650 if (hsotg->params.host_dma) {
652 dev_vdbg(hsotg->dev, "DMA enabled\n");
653 dwc2_hc_enable_dma_ints(hsotg, chan);
656 dev_vdbg(hsotg->dev, "DMA disabled\n");
657 dwc2_hc_enable_slave_ints(hsotg, chan);
661 intmsk = dwc2_readl(hsotg, HAINTMSK);
663 dwc2_writel(hsotg, intmsk, HAINTMSK);
665 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
668 intmsk = dwc2_readl(hsotg, GINTMSK);
670 dwc2_writel(hsotg, intmsk, GINTMSK);
672 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
679 * @hsotg: Programming view of DWC_otg controller
686 static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
694 dev_vdbg(hsotg->dev, "%s()\n", __func__);
699 dwc2_writel(hsotg, hcintmsk, HCINT(hc_num));
702 dwc2_hc_enable_ints(hsotg, chan);
716 dwc2_writel(hsotg, hcchar, HCCHAR(hc_num));
718 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
721 dev_vdbg(hsotg->dev, "%s: Channel %d\n",
723 dev_vdbg(hsotg->dev, " Dev Addr: %d\n",
725 dev_vdbg(hsotg->dev, " Ep Num: %d\n",
727 dev_vdbg(hsotg->dev, " Is In: %d\n",
729 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n",
731 dev_vdbg(hsotg->dev, " Ep Type: %d\n",
733 dev_vdbg(hsotg->dev, " Max Pkt: %d\n",
740 dev_vdbg(hsotg->dev,
753 dev_vdbg(hsotg->dev, " comp split %d\n",
755 dev_vdbg(hsotg->dev, " xact pos %d\n",
757 dev_vdbg(hsotg->dev, " hub addr %d\n",
759 dev_vdbg(hsotg->dev, " hub port %d\n",
761 dev_vdbg(hsotg->dev, " is_in %d\n",
763 dev_vdbg(hsotg->dev, " Max Pkt %d\n",
765 dev_vdbg(hsotg->dev, " xferlen %d\n",
770 dwc2_writel(hsotg, hcsplt, HCSPLT(hc_num));
776 * @hsotg: Controller register interface
801 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
807 dev_vdbg(hsotg->dev, "%s()\n", __func__);
815 if ((hsotg->params.g_dma && !hsotg->params.g_dma_desc) ||
816 hsotg->hw_params.arch == GHWCFG2_EXT_DMA_ARCH) {
820 dev_err(hsotg->dev, "%s() Channel can't be halted\n",
827 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status);
839 dev_vdbg(hsotg->dev, "dequeue/error\n");
840 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
847 dwc2_writel(hsotg, ~hcintmsk, HCINT(chan->hc_num));
856 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
878 dev_vdbg(hsotg->dev,
884 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
888 if (!hsotg->params.dma_desc_enable) {
890 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
894 dev_dbg(hsotg->dev, "desc DMA enabled\n");
898 if (!hsotg->params.host_dma) {
900 dev_vdbg(hsotg->dev, "DMA not enabled\n");
906 dev_vdbg(hsotg->dev, "control/bulk\n");
907 nptxsts = dwc2_readl(hsotg, GNPTXSTS);
909 dev_vdbg(hsotg->dev, "Disabling channel\n");
914 dev_vdbg(hsotg->dev, "isoc/intr\n");
915 hptxsts = dwc2_readl(hsotg, HPTXSTS);
917 hsotg->queuing_high_bandwidth) {
919 dev_vdbg(hsotg->dev, "Disabling channel\n");
925 dev_vdbg(hsotg->dev, "DMA enabled\n");
928 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
933 dev_vdbg(hsotg->dev, "Channel enabled\n");
938 dev_vdbg(hsotg->dev, "Channel disabled\n");
943 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
945 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n",
947 dev_vdbg(hsotg->dev, " halt_pending: %d\n",
949 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n",
951 dev_vdbg(hsotg->dev, " halt_status: %d\n",
959 * @hsotg: Programming view of DWC_otg controller
965 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
977 dwc2_writel(hsotg, 0, HCINTMSK(chan->hc_num));
980 dwc2_writel(hsotg, hcintmsk, HCINT(chan->hc_num));
987 * @hsotg: Programming view of DWC_otg controller
993 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
1034 fifo_space = (dwc2_readl(hsotg, HPTXSTS) &
1037 (hsotg->params.host_perio_tx_fifo_size -
1053 frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us);
1066 dwc2_sch_vdbg(hsotg,
1118 * @hsotg: Programming view of DWC_otg controller
1128 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg,
1138 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1151 dwc2_writel(hsotg, *data_buf, HCFIFO(chan->hc_num));
1157 dwc2_writel(hsotg, data, HCFIFO(chan->hc_num));
1168 * @hsotg: Programming view of DWC_otg controller
1174 static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
1181 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1186 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1188 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1191 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1198 * @hsotg: Programming view of DWC_otg controller
1227 static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1230 u32 max_hc_xfer_size = hsotg->params.max_transfer_size;
1231 u16 max_hc_pkt_count = hsotg->params.max_packet_count;
1238 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1241 if (!hsotg->params.host_dma) {
1243 dev_vdbg(hsotg->dev, "ping, no DMA\n");
1244 dwc2_hc_do_ping(hsotg, chan);
1250 dev_vdbg(hsotg->dev, "ping, DMA\n");
1257 dev_vdbg(hsotg->dev, "split\n");
1282 dev_vdbg(hsotg->dev, "no split\n");
1352 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1354 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
1357 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1359 dev_vdbg(hsotg->dev, " Xfer Size: %d\n",
1362 dev_vdbg(hsotg->dev, " Num Pkts: %d\n",
1365 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1370 if (hsotg->params.host_dma) {
1375 dev_vdbg(hsotg->dev, "align_buf\n");
1380 dwc2_writel(hsotg, (u32)dma_addr, HCDMA(chan->hc_num));
1383 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
1389 u32 hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num));
1392 dwc2_writel(hsotg, hcsplt, HCSPLT(chan->hc_num));
1395 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1398 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1401 dev_warn(hsotg->dev,
1410 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1414 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1416 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1422 if (!hsotg->params.host_dma &&
1425 dwc2_hc_write_packet(hsotg, chan);
1432 * @hsotg: Programming view of DWC_otg controller
1442 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
1465 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1467 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1469 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1);
1472 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1474 dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr,
1477 dwc2_writel(hsotg, chan->desc_list_addr, HCDMA(chan->hc_num));
1480 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n",
1483 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1489 dev_warn(hsotg->dev,
1498 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1502 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1504 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1515 * @hsotg: Programming view of DWC_otg controller
1531 static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
1535 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1559 u32 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1561 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1565 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n",
1567 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1577 u32 hcchar = dwc2_readl(hsotg,
1580 dwc2_hc_set_even_odd_frame(hsotg, chan,
1585 dwc2_hc_write_packet(hsotg, chan);
1605 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
1614 dwc2_host_complete(hsotg, qtd, -ECONNRESET);
1615 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1620 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
1631 spin_lock_irqsave(&hsotg->lock, flags);
1634 dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
1637 dwc2_hcd_qh_unlink(hsotg, qh);
1642 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1647 spin_unlock_irqrestore(&hsotg->lock, flags);
1648 dwc2_hcd_qh_free(hsotg, qh);
1649 spin_lock_irqsave(&hsotg->lock, flags);
1652 spin_unlock_irqrestore(&hsotg->lock, flags);
1663 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
1665 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
1666 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_waiting);
1667 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
1668 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
1669 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
1670 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
1671 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
1677 * @hsotg: Pointer to struct dwc2_hsotg
1679 void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
1683 if (hsotg->op_state == OTG_STATE_B_HOST) {
1689 hprt0 = dwc2_read_hprt0(hsotg);
1691 dwc2_writel(hsotg, hprt0, HPRT0);
1694 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
1699 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
1701 int num_channels = hsotg->params.host_channels;
1706 if (!hsotg->params.host_dma) {
1709 channel = hsotg->hc_ptr_array[i];
1712 hcchar = dwc2_readl(hsotg, HCCHAR(i));
1716 dwc2_writel(hsotg, hcchar, HCCHAR(i));
1722 channel = hsotg->hc_ptr_array[i];
1725 hcchar = dwc2_readl(hsotg, HCCHAR(i));
1729 dwc2_writel(hsotg, hcchar, HCCHAR(i));
1732 dwc2_hc_cleanup(hsotg, channel);
1733 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
1742 if (hsotg->params.uframe_sched) {
1743 hsotg->available_host_channels =
1744 hsotg->params.host_channels;
1746 hsotg->non_periodic_channels = 0;
1747 hsotg->periodic_channels = 0;
1754 * @hsotg: Pointer to struct dwc2_hsotg
1758 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg)
1760 if (hsotg->lx_state != DWC2_L0)
1761 usb_hcd_resume_root_hub(hsotg->priv);
1763 hsotg->flags.b.port_connect_status_change = 1;
1764 hsotg->flags.b.port_connect_status = 1;
1770 * @hsotg: Pointer to struct dwc2_hsotg
1775 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force)
1781 hsotg->flags.b.port_connect_status_change = 1;
1782 hsotg->flags.b.port_connect_status = 0;
1789 intr = dwc2_readl(hsotg, GINTMSK);
1791 dwc2_writel(hsotg, intr, GINTMSK);
1793 dwc2_writel(hsotg, intr, GINTSTS);
1800 if (dwc2_is_device_mode(hsotg)) {
1801 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
1802 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
1803 dwc2_writel(hsotg, 0, HPRT0);
1806 dwc2_disable_host_interrupts(hsotg);
1810 dwc2_kill_all_urbs(hsotg);
1812 if (dwc2_is_host_mode(hsotg))
1814 dwc2_hcd_cleanup_channels(hsotg);
1816 dwc2_host_disconnect(hsotg);
1831 hprt0 = dwc2_readl(hsotg, HPRT0);
1833 dwc2_hcd_connect(hsotg);
1840 * @hsotg: Pointer to struct dwc2_hsotg
1842 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
1844 if (hsotg->bus_suspended) {
1845 hsotg->flags.b.port_suspend_change = 1;
1846 usb_hcd_resume_root_hub(hsotg->priv);
1849 if (hsotg->lx_state == DWC2_L1)
1850 hsotg->flags.b.port_l1_change = 1;
1856 * @hsotg: Pointer to struct dwc2_hsotg
1860 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
1862 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
1871 dwc2_disable_host_interrupts(hsotg);
1874 dev_dbg(hsotg->dev, "PortPower off\n");
1875 dwc2_writel(hsotg, 0, HPRT0);
1879 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
1887 if (!hsotg->flags.b.port_connect_status) {
1889 dev_err(hsotg->dev, "Not connected\n");
1893 dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
1897 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
1898 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
1899 u32 hprt0 = dwc2_readl(hsotg, HPRT0);
1910 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh);
1912 dev_err(hsotg->dev,
1918 intr_mask = dwc2_readl(hsotg, GINTMSK);
1930 tr_type = dwc2_hcd_select_transactions(hsotg);
1932 dwc2_hcd_queue_transactions(hsotg, tr_type);
1939 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
1947 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
1953 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
1960 dwc2_dump_channel_info(hsotg, qh->channel);
1963 if (hsotg->flags.b.port_connect_status)
1971 dwc2_hc_halt(hsotg, qh->channel,
1979 if (!hsotg->params.dma_desc_enable) {
1982 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
1984 dwc2_hcd_qh_deactivate(hsotg, qh, 0);
1987 dwc2_hcd_qh_unlink(hsotg, qh);
1990 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
1997 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
2005 spin_lock_irqsave(&hsotg->lock, flags);
2015 dev_err(hsotg->dev,
2021 spin_unlock_irqrestore(&hsotg->lock, flags);
2023 spin_lock_irqsave(&hsotg->lock, flags);
2031 dwc2_hcd_qh_unlink(hsotg, qh);
2035 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
2042 spin_unlock_irqrestore(&hsotg->lock, flags);
2044 dwc2_hcd_qh_free(hsotg, qh);
2050 spin_unlock_irqrestore(&hsotg->lock, flags);
2056 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
2073 * @hsotg: Programming view of the DWC_otg controller
2076 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
2081 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2083 usbcfg = dwc2_readl(hsotg, GUSBCFG);
2087 if (hsotg->params.phy_ulpi_ext_vbus)
2092 if (hsotg->params.ts_dline)
2095 dwc2_writel(hsotg, usbcfg, GUSBCFG);
2105 retval = dwc2_core_reset(hsotg, false);
2107 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n",
2116 retval = dwc2_phy_init(hsotg, initial_setup);
2121 retval = dwc2_gahbcfg_init(hsotg);
2126 dwc2_gusbcfg_init(hsotg);
2129 otgctl = dwc2_readl(hsotg, GOTGCTL);
2131 dwc2_writel(hsotg, otgctl, GOTGCTL);
2134 hsotg->srp_success = 0;
2137 dwc2_enable_common_interrupts(hsotg);
2143 if (dwc2_is_host_mode(hsotg)) {
2144 dev_dbg(hsotg->dev, "Host Mode\n");
2145 hsotg->op_state = OTG_STATE_A_HOST;
2147 dev_dbg(hsotg->dev, "Device Mode\n");
2148 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
2158 * @hsotg: Programming view of DWC_otg controller
2164 static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
2168 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2178 usbcfg = dwc2_readl(hsotg, GUSBCFG);
2180 dwc2_writel(hsotg, usbcfg, GUSBCFG);
2183 dwc2_writel(hsotg, 0, PCGCTL);
2186 dwc2_init_fs_ls_pclk_sel(hsotg);
2187 if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
2188 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) {
2189 hcfg = dwc2_readl(hsotg, HCFG);
2191 dwc2_writel(hsotg, hcfg, HCFG);
2199 if (hsotg->params.reload_ctl) {
2200 hfir = dwc2_readl(hsotg, HFIR);
2202 dwc2_writel(hsotg, hfir, HFIR);
2205 if (hsotg->params.dma_desc_enable) {
2206 u32 op_mode = hsotg->hw_params.op_mode;
2208 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a ||
2209 !hsotg->hw_params.dma_desc_enable ||
2213 dev_err(hsotg->dev,
2215 dev_err(hsotg->dev,
2217 hsotg->params.dma_desc_enable = false;
2219 hcfg = dwc2_readl(hsotg, HCFG);
2221 dwc2_writel(hsotg, hcfg, HCFG);
2226 dwc2_config_fifos(hsotg);
2230 otgctl = dwc2_readl(hsotg, GOTGCTL);
2232 dwc2_writel(hsotg, otgctl, GOTGCTL);
2235 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
2236 dwc2_flush_rx_fifo(hsotg);
2239 otgctl = dwc2_readl(hsotg, GOTGCTL);
2241 dwc2_writel(hsotg, otgctl, GOTGCTL);
2243 if (!hsotg->params.dma_desc_enable) {
2248 num_channels = hsotg->params.host_channels;
2250 hcchar = dwc2_readl(hsotg, HCCHAR(i));
2255 dwc2_writel(hsotg, hcchar, HCCHAR(i));
2261 hcchar = dwc2_readl(hsotg, HCCHAR(i));
2265 dwc2_writel(hsotg, hcchar, HCCHAR(i));
2266 dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
2269 if (dwc2_hsotg_wait_bit_clear(hsotg, HCCHAR(i),
2272 dev_warn(hsotg->dev,
2281 dwc2_enable_acg(hsotg);
2284 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state);
2285 if (hsotg->op_state == OTG_STATE_A_HOST) {
2286 u32 hprt0 = dwc2_read_hprt0(hsotg);
2288 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n",
2292 dwc2_writel(hsotg, hprt0, HPRT0);
2296 dwc2_enable_host_interrupts(hsotg);
2304 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
2310 hsotg->flags.d32 = 0;
2311 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
2313 if (hsotg->params.uframe_sched) {
2314 hsotg->available_host_channels =
2315 hsotg->params.host_channels;
2317 hsotg->non_periodic_channels = 0;
2318 hsotg->periodic_channels = 0;
2325 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
2329 num_channels = hsotg->params.host_channels;
2331 chan = hsotg->hc_ptr_array[i];
2332 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
2333 dwc2_hc_cleanup(hsotg, chan);
2337 dwc2_core_host_init(hsotg);
2340 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
2349 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
2354 static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
2367 dev_vdbg(hsotg->dev, " Control setup transaction\n");
2371 if (hsotg->params.host_dma)
2379 dev_vdbg(hsotg->dev, " Control data transaction\n");
2388 dev_vdbg(hsotg->dev, " Control status transaction\n");
2398 if (hsotg->params.host_dma)
2399 chan->xfer_dma = hsotg->status_buf_dma;
2401 chan->xfer_buf = hsotg->status_buf;
2416 if (hsotg->params.dma_desc_enable)
2422 if (hsotg->params.host_dma) {
2444 static int dwc2_alloc_split_dma_aligned_buf(struct dwc2_hsotg *hsotg,
2448 if (!hsotg->unaligned_cache ||
2453 qh->dw_align_buf = kmem_cache_alloc(hsotg->unaligned_cache,
2459 qh->dw_align_buf_dma = dma_map_single(hsotg->dev, qh->dw_align_buf,
2463 if (dma_mapping_error(hsotg->dev, qh->dw_align_buf_dma)) {
2464 dev_err(hsotg->dev, "can't map align_buf\n");
2575 * @hsotg: The HCD state structure
2579 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
2586 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
2589 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
2593 if (list_empty(&hsotg->free_hc_list)) {
2594 dev_dbg(hsotg->dev, "No free channel to assign\n");
2598 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
2645 if (hsotg->params.host_dma)
2655 dwc2_hc_init_split(hsotg, chan, qtd, urb);
2660 dwc2_hc_init_xfer(hsotg, chan, qtd);
2663 if (hsotg->params.host_dma && qh->do_split &&
2665 dev_vdbg(hsotg->dev, "Non-aligned buffer\n");
2666 if (dwc2_alloc_split_dma_aligned_buf(hsotg, qh, chan)) {
2667 dev_err(hsotg->dev,
2673 &hsotg->free_hc_list);
2683 WARN_ON_ONCE(hsotg->params.host_dma &&
2696 if (hsotg->params.dma_desc_enable) {
2701 dwc2_hc_init(hsotg, chan);
2712 * @hsotg: The HCD state structure
2717 struct dwc2_hsotg *hsotg)
2725 dev_vdbg(hsotg->dev, " Select Transactions\n");
2729 qh_ptr = hsotg->periodic_sched_ready.next;
2730 while (qh_ptr != &hsotg->periodic_sched_ready) {
2731 if (list_empty(&hsotg->free_hc_list))
2733 if (hsotg->params.uframe_sched) {
2734 if (hsotg->available_host_channels <= 1)
2736 hsotg->available_host_channels--;
2739 if (dwc2_assign_and_init_hc(hsotg, qh))
2748 &hsotg->periodic_sched_assigned);
2757 num_channels = hsotg->params.host_channels;
2758 qh_ptr = hsotg->non_periodic_sched_inactive.next;
2759 while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
2760 if (!hsotg->params.uframe_sched &&
2761 hsotg->non_periodic_channels >= num_channels -
2762 hsotg->periodic_channels)
2764 if (list_empty(&hsotg->free_hc_list))
2767 if (hsotg->params.uframe_sched) {
2768 if (hsotg->available_host_channels < 1)
2770 hsotg->available_host_channels--;
2773 if (dwc2_assign_and_init_hc(hsotg, qh))
2782 &hsotg->non_periodic_sched_active);
2789 if (!hsotg->params.uframe_sched)
2790 hsotg->non_periodic_channels++;
2800 * @hsotg: The HCD state structure
2817 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
2826 &hsotg->split_order);
2828 if (hsotg->params.host_dma && chan->qh) {
2829 if (hsotg->params.dma_desc_enable) {
2832 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
2836 dwc2_hc_start_transfer(hsotg, chan);
2842 dwc2_hc_halt(hsotg, chan, chan->halt_status);
2845 dwc2_hc_start_transfer(hsotg, chan);
2850 dwc2_hc_start_transfer(hsotg, chan);
2853 retval = dwc2_hc_continue_transfer(hsotg, chan);
2860 dwc2_hc_start_transfer(hsotg, chan);
2863 retval = dwc2_hc_continue_transfer(hsotg, chan);
2879 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
2892 if (list_empty(&hsotg->periodic_sched_assigned))
2896 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
2898 tx_status = dwc2_readl(hsotg, HPTXSTS);
2905 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n",
2907 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n",
2911 qh_ptr = hsotg->periodic_sched_assigned.next;
2912 while (qh_ptr != &hsotg->periodic_sched_assigned) {
2913 tx_status = dwc2_readl(hsotg, HPTXSTS);
2938 if (!hsotg->params.host_dma &&
2940 hsotg->queuing_high_bandwidth = 1;
2944 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
2957 if (hsotg->params.host_dma || status == 0 ||
2965 &hsotg->periodic_sched_queued);
2968 hsotg->queuing_high_bandwidth = 0;
2974 (!hsotg->params.host_dma &&
2975 !list_empty(&hsotg->periodic_sched_assigned))) {
2983 gintmsk = dwc2_readl(hsotg, GINTMSK);
2986 dwc2_writel(hsotg, gintmsk, GINTMSK);
2996 gintmsk = dwc2_readl(hsotg, GINTMSK);
2999 dwc2_writel(hsotg, gintmsk, GINTMSK);
3013 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
3026 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
3028 tx_status = dwc2_readl(hsotg, GNPTXSTS);
3033 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n",
3035 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n",
3042 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
3043 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3044 orig_qh_ptr = hsotg->non_periodic_qh_ptr;
3051 tx_status = dwc2_readl(hsotg, GNPTXSTS);
3054 if (!hsotg->params.host_dma && qspcavail == 0) {
3059 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
3070 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
3080 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3081 if (hsotg->non_periodic_qh_ptr ==
3082 &hsotg->non_periodic_sched_active)
3083 hsotg->non_periodic_qh_ptr =
3084 hsotg->non_periodic_qh_ptr->next;
3085 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
3087 if (!hsotg->params.host_dma) {
3088 tx_status = dwc2_readl(hsotg, GNPTXSTS);
3093 dev_vdbg(hsotg->dev,
3096 dev_vdbg(hsotg->dev,
3108 gintmsk = dwc2_readl(hsotg, GINTMSK);
3110 dwc2_writel(hsotg, gintmsk, GINTMSK);
3119 gintmsk = dwc2_readl(hsotg, GINTMSK);
3121 dwc2_writel(hsotg, gintmsk, GINTMSK);
3131 * @hsotg: The HCD state structure
3137 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
3141 dev_vdbg(hsotg->dev, "Queue Transactions\n");
3146 dwc2_process_periodic_channels(hsotg);
3151 if (!list_empty(&hsotg->non_periodic_sched_active)) {
3152 dwc2_process_non_periodic_channels(hsotg);
3158 u32 gintmsk = dwc2_readl(hsotg, GINTMSK);
3161 dwc2_writel(hsotg, gintmsk, GINTMSK);
3168 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
3174 dev_dbg(hsotg->dev, "%s()\n", __func__);
3176 gotgctl = dwc2_readl(hsotg, GOTGCTL);
3177 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
3178 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
3183 dwc2_vbus_supply_exit(hsotg);
3185 dev_dbg(hsotg->dev, "connId B\n");
3186 if (hsotg->bus_suspended) {
3187 dev_info(hsotg->dev,
3189 dwc2_port_resume(hsotg);
3191 while (!dwc2_is_device_mode(hsotg)) {
3192 dev_info(hsotg->dev,
3194 dwc2_is_host_mode(hsotg) ? "Host" :
3202 gotgctl = dwc2_readl(hsotg, GOTGCTL);
3209 dev_err(hsotg->dev,
3211 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3212 dwc2_core_init(hsotg, false);
3213 dwc2_enable_global_interrupts(hsotg);
3214 spin_lock_irqsave(&hsotg->lock, flags);
3215 dwc2_hsotg_core_init_disconnected(hsotg, false);
3216 spin_unlock_irqrestore(&hsotg->lock, flags);
3218 dwc2_enable_acg(hsotg);
3219 dwc2_hsotg_core_connect(hsotg);
3223 dev_dbg(hsotg->dev, "connId A\n");
3224 while (!dwc2_is_host_mode(hsotg)) {
3225 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
3226 dwc2_is_host_mode(hsotg) ?
3233 dev_err(hsotg->dev,
3236 spin_lock_irqsave(&hsotg->lock, flags);
3237 dwc2_hsotg_disconnect(hsotg);
3238 spin_unlock_irqrestore(&hsotg->lock, flags);
3240 hsotg->op_state = OTG_STATE_A_HOST;
3242 dwc2_core_init(hsotg, false);
3243 dwc2_enable_global_interrupts(hsotg);
3244 dwc2_hcd_start(hsotg);
3250 struct dwc2_hsotg *hsotg = from_timer(hsotg, t, wkp_timer);
3253 dev_dbg(hsotg->dev, "%s()\n", __func__);
3259 hprt0 = dwc2_read_hprt0(hsotg);
3260 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
3262 dwc2_writel(hsotg, hprt0, HPRT0);
3263 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
3264 dwc2_readl(hsotg, HPRT0));
3266 dwc2_hcd_rem_wakeup(hsotg);
3267 hsotg->bus_suspended = false;
3270 hsotg->lx_state = DWC2_L0;
3273 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
3275 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
3281 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
3288 dev_dbg(hsotg->dev, "%s()\n", __func__);
3290 spin_lock_irqsave(&hsotg->lock, flags);
3292 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
3293 gotgctl = dwc2_readl(hsotg, GOTGCTL);
3295 dwc2_writel(hsotg, gotgctl, GOTGCTL);
3296 hsotg->op_state = OTG_STATE_A_SUSPEND;
3299 hprt0 = dwc2_read_hprt0(hsotg);
3301 dwc2_writel(hsotg, hprt0, HPRT0);
3303 hsotg->bus_suspended = true;
3309 if (!hsotg->params.power_down) {
3311 pcgctl = dwc2_readl(hsotg, PCGCTL);
3313 dwc2_writel(hsotg, pcgctl, PCGCTL);
3318 if (dwc2_host_is_b_hnp_enabled(hsotg)) {
3319 pcgctl = dwc2_readl(hsotg, PCGCTL);
3321 dwc2_writel(hsotg, pcgctl, PCGCTL);
3323 spin_unlock_irqrestore(&hsotg->lock, flags);
3327 spin_unlock_irqrestore(&hsotg->lock, flags);
3332 static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
3338 spin_lock_irqsave(&hsotg->lock, flags);
3344 if (!hsotg->params.power_down) {
3345 pcgctl = dwc2_readl(hsotg, PCGCTL);
3347 dwc2_writel(hsotg, pcgctl, PCGCTL);
3348 spin_unlock_irqrestore(&hsotg->lock, flags);
3350 spin_lock_irqsave(&hsotg->lock, flags);
3353 hprt0 = dwc2_read_hprt0(hsotg);
3356 dwc2_writel(hsotg, hprt0, HPRT0);
3357 spin_unlock_irqrestore(&hsotg->lock, flags);
3361 spin_lock_irqsave(&hsotg->lock, flags);
3362 hprt0 = dwc2_read_hprt0(hsotg);
3364 dwc2_writel(hsotg, hprt0, HPRT0);
3365 hsotg->bus_suspended = false;
3366 spin_unlock_irqrestore(&hsotg->lock, flags);
3370 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3383 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
3393 dev_err(hsotg->dev,
3405 dev_dbg(hsotg->dev,
3407 hprt0 = dwc2_read_hprt0(hsotg);
3409 dwc2_writel(hsotg, hprt0, HPRT0);
3413 dev_dbg(hsotg->dev,
3416 if (hsotg->bus_suspended) {
3417 if (hsotg->hibernated)
3418 dwc2_exit_hibernation(hsotg, 0, 0, 1);
3420 dwc2_port_resume(hsotg);
3425 dev_dbg(hsotg->dev,
3427 hprt0 = dwc2_read_hprt0(hsotg);
3430 dwc2_writel(hsotg, hprt0, HPRT0);
3432 dwc2_vbus_supply_exit(hsotg);
3436 dev_dbg(hsotg->dev,
3445 dev_dbg(hsotg->dev,
3447 hsotg->flags.b.port_connect_status_change = 0;
3452 dev_dbg(hsotg->dev,
3454 hsotg->flags.b.port_reset_change = 0;
3462 dev_dbg(hsotg->dev,
3464 hsotg->flags.b.port_enable_change = 0;
3473 dev_dbg(hsotg->dev,
3475 hsotg->flags.b.port_suspend_change = 0;
3479 dev_dbg(hsotg->dev,
3481 hsotg->flags.b.port_l1_change = 0;
3485 dev_dbg(hsotg->dev,
3487 hsotg->flags.b.port_over_current_change = 0;
3492 dev_err(hsotg->dev,
3499 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
3514 dev_dbg(hsotg->dev, "GetHubStatus\n");
3519 dev_vdbg(hsotg->dev,
3521 hsotg->flags.d32);
3526 if (hsotg->flags.b.port_connect_status_change)
3528 if (hsotg->flags.b.port_enable_change)
3530 if (hsotg->flags.b.port_suspend_change)
3532 if (hsotg->flags.b.port_l1_change)
3534 if (hsotg->flags.b.port_reset_change)
3536 if (hsotg->flags.b.port_over_current_change) {
3537 dev_warn(hsotg->dev, "Overcurrent change detected\n");
3541 if (!hsotg->flags.b.port_connect_status) {
3553 hprt0 = dwc2_readl(hsotg, HPRT0);
3554 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0);
3579 if (hsotg->params.dma_desc_fs_enable) {
3584 if (hsotg->new_connection &&
3592 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n");
3593 hsotg->params.dma_desc_enable = true;
3594 hcfg = dwc2_readl(hsotg, HCFG);
3596 dwc2_writel(hsotg, hcfg, HCFG);
3597 hsotg->new_connection = false;
3601 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
3606 dev_dbg(hsotg->dev, "SetHubFeature\n");
3611 dev_dbg(hsotg->dev, "SetPortFeature\n");
3615 if (!hsotg->flags.b.port_connect_status) {
3628 dev_dbg(hsotg->dev,
3630 if (windex != hsotg->otg_port)
3632 if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_HIBERNATION)
3633 dwc2_enter_hibernation(hsotg, 1);
3635 dwc2_port_suspend(hsotg, windex);
3639 dev_dbg(hsotg->dev,
3641 hprt0 = dwc2_read_hprt0(hsotg);
3644 dwc2_writel(hsotg, hprt0, HPRT0);
3646 dwc2_vbus_supply_init(hsotg);
3650 if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_HIBERNATION &&
3651 hsotg->hibernated)
3652 dwc2_exit_hibernation(hsotg, 0, 1, 1);
3653 hprt0 = dwc2_read_hprt0(hsotg);
3654 dev_dbg(hsotg->dev,
3656 pcgctl = dwc2_readl(hsotg, PCGCTL);
3658 dwc2_writel(hsotg, pcgctl, PCGCTL);
3660 dwc2_writel(hsotg, 0, PCGCTL);
3662 hprt0 = dwc2_read_hprt0(hsotg);
3672 if (!dwc2_hcd_is_b_host(hsotg)) {
3674 dev_dbg(hsotg->dev,
3676 dwc2_writel(hsotg, hprt0, HPRT0);
3678 dwc2_vbus_supply_init(hsotg);
3684 dwc2_writel(hsotg, hprt0, HPRT0);
3685 hsotg->lx_state = DWC2_L0; /* Now back to On state */
3689 dev_dbg(hsotg->dev,
3695 hprt0 = dwc2_read_hprt0(hsotg);
3696 dev_dbg(hsotg->dev,
3700 dwc2_writel(hsotg, hprt0, HPRT0);
3705 dev_err(hsotg->dev,
3715 dev_dbg(hsotg->dev,
3724 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
3731 retval = (hsotg->flags.b.port_connect_status_change ||
3732 hsotg->flags.b.port_reset_change ||
3733 hsotg->flags.b.port_enable_change ||
3734 hsotg->flags.b.port_suspend_change ||
3735 hsotg->flags.b.port_over_current_change);
3738 dev_dbg(hsotg->dev,
3740 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n",
3741 hsotg->flags.b.port_connect_status_change);
3742 dev_dbg(hsotg->dev, " port_reset_change: %d\n",
3743 hsotg->flags.b.port_reset_change);
3744 dev_dbg(hsotg->dev, " port_enable_change: %d\n",
3745 hsotg->flags.b.port_enable_change);
3746 dev_dbg(hsotg->dev, " port_suspend_change: %d\n",
3747 hsotg->flags.b.port_suspend_change);
3748 dev_dbg(hsotg->dev, " port_over_current_change: %d\n",
3749 hsotg->flags.b.port_over_current_change);
3755 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
3757 u32 hfnum = dwc2_readl(hsotg, HFNUM);
3760 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
3766 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us)
3768 u32 hprt = dwc2_readl(hsotg, HPRT0);
3769 u32 hfir = dwc2_readl(hsotg, HFIR);
3770 u32 hfnum = dwc2_readl(hsotg, HFNUM);
3795 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
3797 return hsotg->op_state == OTG_STATE_B_HOST;
3800 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
3812 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
3820 dev_vdbg(hsotg->dev,
3835 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
3846 num_channels = hsotg->params.host_channels;
3847 dev_dbg(hsotg->dev, "\n");
3848 dev_dbg(hsotg->dev,
3850 dev_dbg(hsotg->dev, "HCD State:\n");
3851 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels);
3854 chan = hsotg->hc_ptr_array[i];
3855 dev_dbg(hsotg->dev, " Channel %d:\n", i);
3856 dev_dbg(hsotg->dev,
3859 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed);
3860 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
3861 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
3862 dev_dbg(hsotg->dev, " data_pid_start: %d\n",
3864 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count);
3865 dev_dbg(hsotg->dev, " xfer_started: %d\n",
3867 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
3868 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
3870 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
3871 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count);
3872 dev_dbg(hsotg->dev, " halt_on_queue: %d\n",
3874 dev_dbg(hsotg->dev, " halt_pending: %d\n",
3876 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
3877 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split);
3878 dev_dbg(hsotg->dev, " complete_split: %d\n",
3880 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr);
3881 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port);
3882 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos);
3883 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests);
3884 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
3889 hfnum = dwc2_readl(hsotg, HFNUM);
3890 hcchar = dwc2_readl(hsotg, HCCHAR(i));
3891 hctsiz = dwc2_readl(hsotg, HCTSIZ(i));
3892 hcint = dwc2_readl(hsotg, HCINT(i));
3893 hcintmsk = dwc2_readl(hsotg, HCINTMSK(i));
3894 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum);
3895 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar);
3896 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz);
3897 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint);
3898 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk);
3908 dev_dbg(hsotg->dev, " URB Info:\n");
3909 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n",
3912 dev_dbg(hsotg->dev,
3918 dev_dbg(hsotg->dev,
3922 dev_dbg(hsotg->dev,
3925 dev_dbg(hsotg->dev,
3928 dev_dbg(hsotg->dev,
3931 dev_dbg(hsotg->dev, " actual_length: %d\n",
3937 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n",
3938 hsotg->non_periodic_channels);
3939 dev_dbg(hsotg->dev, " periodic_channels: %d\n",
3940 hsotg->periodic_channels);
3941 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs);
3942 np_tx_status = dwc2_readl(hsotg, GNPTXSTS);
3943 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n",
3945 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n",
3947 p_tx_status = dwc2_readl(hsotg, HPTXSTS);
3948 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n",
3950 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n",
3952 dwc2_dump_global_registers(hsotg);
3953 dwc2_dump_host_registers(hsotg);
3954 dev_dbg(hsotg->dev,
3956 dev_dbg(hsotg->dev, "\n");
3961 struct dwc2_hsotg *hsotg;
3970 return p->hsotg;
3983 * @hsotg: The HCD state structure for the DWC OTG controller.
3993 struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context,
4038 * @hsotg: The HCD state structure for the DWC OTG controller.
4041 void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt)
4056 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
4095 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
4102 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
4107 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
4113 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
4120 dev_vdbg(hsotg->dev,
4140 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
4156 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
4157 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4161 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
4166 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
4174 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4177 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
4178 dwc2_host_start(hsotg);
4186 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4191 dev_dbg(hsotg->dev, "USB RESET function called\n");
4193 spin_lock_irqsave(&hsotg->lock, flags);
4195 hprt0 = dwc2_read_hprt0(hsotg);
4197 dwc2_writel(hsotg, hprt0, HPRT0);
4198 hsotg->flags.b.port_reset_change = 1;
4200 spin_unlock_irqrestore(&hsotg->lock, flags);
4205 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4209 ret = phy_reset(hsotg->phy);
4211 dev_warn(hsotg->dev, "PHY reset failed\n");
4227 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4233 dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
4235 spin_lock_irqsave(&hsotg->lock, flags);
4236 hsotg->lx_state = DWC2_L0;
4240 if (dwc2_is_device_mode(hsotg)) {
4241 spin_unlock_irqrestore(&hsotg->lock, flags);
4245 dwc2_hcd_reinit(hsotg);
4247 hprt0 = dwc2_read_hprt0(hsotg);
4251 spin_unlock_irqrestore(&hsotg->lock, flags);
4252 ret = dwc2_vbus_supply_init(hsotg);
4255 spin_lock_irqsave(&hsotg->lock, flags);
4260 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
4265 spin_unlock_irqrestore(&hsotg->lock, flags);
4276 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4281 dwc2_disable_host_interrupts(hsotg);
4286 spin_lock_irqsave(&hsotg->lock, flags);
4287 hprt0 = dwc2_read_hprt0(hsotg);
4289 dwc2_hcd_disconnect(hsotg, true);
4290 dwc2_hcd_stop(hsotg);
4291 hsotg->lx_state = DWC2_L3;
4294 spin_unlock_irqrestore(&hsotg->lock, flags);
4298 dwc2_vbus_supply_exit(hsotg);
4305 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4311 spin_lock_irqsave(&hsotg->lock, flags);
4313 if (dwc2_is_device_mode(hsotg))
4316 if (hsotg->lx_state != DWC2_L0)
4322 if (hsotg->op_state == OTG_STATE_B_PERIPHERAL)
4325 if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL ||
4326 hsotg->flags.b.port_connect_status == 0)
4333 if (!hsotg->bus_suspended) {
4334 hprt0 = dwc2_read_hprt0(hsotg);
4337 if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL)
4339 dwc2_writel(hsotg, hprt0, HPRT0);
4341 if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) {
4342 spin_unlock_irqrestore(&hsotg->lock, flags);
4343 dwc2_vbus_supply_exit(hsotg);
4344 spin_lock_irqsave(&hsotg->lock, flags);
4346 pcgctl = readl(hsotg->regs + PCGCTL);
4348 writel(pcgctl, hsotg->regs + PCGCTL);
4352 if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) {
4354 ret = dwc2_enter_partial_power_down(hsotg);
4357 dev_err(hsotg->dev,
4367 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4368 spin_unlock_irqrestore(&hsotg->lock, flags);
4369 usb_phy_set_suspend(hsotg->uphy, true);
4370 spin_lock_irqsave(&hsotg->lock, flags);
4374 hsotg->lx_state = DWC2_L2;
4376 spin_unlock_irqrestore(&hsotg->lock, flags);
4383 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4388 spin_lock_irqsave(&hsotg->lock, flags);
4390 if (dwc2_is_device_mode(hsotg))
4393 if (hsotg->lx_state != DWC2_L2)
4396 if (hsotg->params.power_down > DWC2_POWER_DOWN_PARAM_PARTIAL) {
4397 hsotg->lx_state = DWC2_L0;
4406 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4407 spin_unlock_irqrestore(&hsotg->lock, flags);
4408 usb_phy_set_suspend(hsotg->uphy, false);
4409 spin_lock_irqsave(&hsotg->lock, flags);
4412 if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) {
4421 ret = dwc2_exit_partial_power_down(hsotg, true);
4423 dev_err(hsotg->dev, "exit partial_power_down failed\n");
4425 pcgctl = readl(hsotg->regs + PCGCTL);
4427 writel(pcgctl, hsotg->regs + PCGCTL);
4430 hsotg->lx_state = DWC2_L0;
4432 spin_unlock_irqrestore(&hsotg->lock, flags);
4434 if (hsotg->bus_suspended) {
4435 spin_lock_irqsave(&hsotg->lock, flags);
4436 hsotg->flags.b.port_suspend_change = 1;
4437 spin_unlock_irqrestore(&hsotg->lock, flags);
4438 dwc2_port_resume(hsotg);
4440 if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_PARTIAL) {
4441 dwc2_vbus_supply_init(hsotg);
4451 dwc2_writel(hsotg, HPRT0_PWR | HPRT0_CONNDET |
4459 spin_unlock_irqrestore(&hsotg->lock, flags);
4467 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4469 return dwc2_hcd_get_frame_number(hsotg);
4476 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4480 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
4481 dev_vdbg(hsotg->dev, " Device address: %d\n",
4483 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n",
4502 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype,
4521 dev_vdbg(hsotg->dev, " Speed: %s\n", speed);
4522 dev_vdbg(hsotg->dev, " Max packet size: %d (%d mult)\n",
4526 dev_vdbg(hsotg->dev, " Data buffer length: %d\n",
4528 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
4530 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
4532 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval);
4538 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i);
4539 dev_vdbg(hsotg->dev, " offset: %d, length %d\n",
4555 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4570 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
4579 spin_lock_irqsave(&hsotg->lock, flags);
4580 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
4582 spin_unlock_irqrestore(&hsotg->lock, flags);
4600 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
4605 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
4615 dev_err(hsotg->dev,
4647 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags);
4662 spin_lock_irqsave(&hsotg->lock, flags);
4667 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
4673 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4677 spin_unlock_irqrestore(&hsotg->lock, flags);
4688 spin_unlock_irqrestore(&hsotg->lock, flags);
4695 dwc2_hcd_qh_unlink(hsotg, qh);
4699 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh);
4700 dwc2_hcd_qh_free(hsotg, qh);
4714 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4718 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
4721 spin_lock_irqsave(&hsotg->lock, flags);
4728 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
4732 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
4740 spin_unlock(&hsotg->lock);
4742 spin_lock(&hsotg->lock);
4744 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
4745 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status);
4747 spin_unlock_irqrestore(&hsotg->lock, flags);
4760 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4762 dev_dbg(hsotg->dev,
4765 dwc2_hcd_endpoint_disable(hsotg, ep, 250);
4776 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4779 dev_dbg(hsotg->dev,
4783 spin_lock_irqsave(&hsotg->lock, flags);
4784 dwc2_hcd_endpoint_reset(hsotg, ep);
4785 spin_unlock_irqrestore(&hsotg->lock, flags);
4797 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4799 return dwc2_handle_hcd_intr(hsotg);
4810 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4812 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
4829 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4837 spin_lock_irqsave(&hsotg->lock, flags);
4840 if (hsotg->flags.b.port_connect_status)
4841 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
4843 spin_unlock_irqrestore(&hsotg->lock, flags);
4852 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4854 if (hsotg->params.speed == speed)
4857 hsotg->params.speed = speed;
4858 queue_work(hsotg->wq_otg, &hsotg->wf_otg);
4863 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4865 if (!hsotg->params.change_speed_quirk)
4873 dev_info(hsotg->dev, "Set speed to default high-speed\n");
4880 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4882 if (!hsotg->params.change_speed_quirk)
4886 dev_info(hsotg->dev, "Set speed to high-speed\n");
4894 dev_info(hsotg->dev, "Set speed to full-speed\n");
4932 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
4938 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
4941 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
4942 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_waiting);
4943 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
4944 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
4945 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
4946 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
4947 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
4951 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
4954 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
4956 hsotg->hc_ptr_array[i] = NULL;
4961 if (hsotg->params.host_dma) {
4962 if (hsotg->status_buf) {
4963 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
4964 hsotg->status_buf,
4965 hsotg->status_buf_dma);
4966 hsotg->status_buf = NULL;
4969 kfree(hsotg->status_buf);
4970 hsotg->status_buf = NULL;
4973 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
4977 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
4978 dwc2_writel(hsotg, 0, GINTMSK);
4980 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
4981 dctl = dwc2_readl(hsotg, DCTL);
4983 dwc2_writel(hsotg, dctl, DCTL);
4986 if (hsotg->wq_otg) {
4987 if (!cancel_work_sync(&hsotg->wf_otg))
4988 flush_workqueue(hsotg->wq_otg);
4989 destroy_workqueue(hsotg->wq_otg);
4992 cancel_work_sync(&hsotg->phy_reset_work);
4994 del_timer(&hsotg->wkp_timer);
4997 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
5000 dwc2_disable_host_interrupts(hsotg);
5002 dwc2_hcd_free(hsotg);
5011 int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
5013 struct platform_device *pdev = to_platform_device(hsotg->dev);
5024 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
5028 hcfg = dwc2_readl(hsotg, HCFG);
5029 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
5032 hsotg->frame_num_array = kcalloc(FRAME_NUM_ARRAY_SIZE,
5033 sizeof(*hsotg->frame_num_array),
5035 if (!hsotg->frame_num_array)
5037 hsotg->last_frame_num_array =
5039 sizeof(*hsotg->last_frame_num_array), GFP_KERNEL);
5040 if (!hsotg->last_frame_num_array)
5043 hsotg->last_frame_num = HFNUM_MAX_FRNUM;
5046 if (hsotg->params.host_dma &&
5047 !hsotg->dev->dma_mask) {
5048 dev_warn(hsotg->dev,
5050 hsotg->params.host_dma = false;
5051 hsotg->params.dma_desc_enable = false;
5055 if (hsotg->params.host_dma) {
5056 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5057 dev_warn(hsotg->dev, "can't set DMA mask\n");
5058 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5059 dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
5062 if (hsotg->params.change_speed_quirk) {
5067 if (hsotg->params.host_dma)
5070 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
5084 ((struct wrapper_priv_data *)&hcd->hcd_priv)->hsotg = hsotg;
5085 hsotg->priv = hcd;
5091 dwc2_disable_global_interrupts(hsotg);
5094 retval = dwc2_core_init(hsotg, true);
5100 hsotg->wq_otg = alloc_ordered_workqueue("dwc2", 0);
5101 if (!hsotg->wq_otg) {
5102 dev_err(hsotg->dev, "Failed to create workqueue\n");
5105 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
5107 timer_setup(&hsotg->wkp_timer, dwc2_wakeup_detected, 0);
5110 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
5111 INIT_LIST_HEAD(&hsotg->non_periodic_sched_waiting);
5112 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
5115 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
5116 INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
5117 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
5118 INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
5120 INIT_LIST_HEAD(&hsotg->split_order);
5126 INIT_LIST_HEAD(&hsotg->free_hc_list);
5127 num_channels = hsotg->params.host_channels;
5128 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
5136 hsotg->hc_ptr_array[i] = channel;
5140 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
5141 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
5142 INIT_WORK(&hsotg->phy_reset_work, dwc2_hcd_phy_reset_func);
5150 if (hsotg->params.host_dma)
5151 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
5153 &hsotg->status_buf_dma, GFP_KERNEL);
5155 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
5158 if (!hsotg->status_buf)
5166 if (hsotg->params.dma_desc_enable ||
5167 hsotg->params.dma_desc_fs_enable) {
5168 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc",
5172 if (!hsotg->desc_gen_cache) {
5173 dev_err(hsotg->dev,
5180 hsotg->params.dma_desc_enable = false;
5181 hsotg->params.dma_desc_fs_enable = false;
5184 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc",
5187 if (!hsotg->desc_hsisoc_cache) {
5188 dev_err(hsotg->dev,
5191 kmem_cache_destroy(hsotg->desc_gen_cache);
5197 hsotg->params.dma_desc_enable = false;
5198 hsotg->params.dma_desc_fs_enable = false;
5202 if (hsotg->params.host_dma) {
5207 hsotg->unaligned_cache = kmem_cache_create("dwc2-unaligned-dma",
5210 if (!hsotg->unaligned_cache)
5211 dev_err(hsotg->dev,
5215 hsotg->otg_port = 1;
5216 hsotg->frame_list = NULL;
5217 hsotg->frame_list_dma = 0;
5218 hsotg->periodic_qh_count = 0;
5221 hsotg->lx_state = DWC2_L3;
5223 hcd->self.otg_port = hsotg->otg_port;
5228 if (!IS_ERR_OR_NULL(hsotg->uphy))
5229 otg_set_host(hsotg->uphy->otg, &hcd->self);
5236 retval = usb_add_hcd(hcd, hsotg->irq, IRQF_SHARED);
5242 dwc2_hcd_dump_state(hsotg);
5244 dwc2_enable_global_interrupts(hsotg);
5249 kmem_cache_destroy(hsotg->unaligned_cache);
5250 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5251 kmem_cache_destroy(hsotg->desc_gen_cache);
5253 dwc2_hcd_release(hsotg);
5259 kfree(hsotg->last_frame_num_array);
5260 kfree(hsotg->frame_num_array);
5263 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
5271 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
5275 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
5277 hcd = dwc2_hsotg_to_hcd(hsotg);
5278 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
5281 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
5286 if (!IS_ERR_OR_NULL(hsotg->uphy))
5287 otg_set_host(hsotg->uphy->otg, NULL);
5290 hsotg->priv = NULL;
5292 kmem_cache_destroy(hsotg->unaligned_cache);
5293 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5294 kmem_cache_destroy(hsotg->desc_gen_cache);
5296 dwc2_hcd_release(hsotg);
5300 kfree(hsotg->last_frame_num_array);
5301 kfree(hsotg->frame_num_array);
5310 * @hsotg: Programming view of the DWC_otg controller
5312 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
5317 dev_dbg(hsotg->dev, "%s\n", __func__);
5320 hr = &hsotg->hr_backup;
5321 hr->hcfg = dwc2_readl(hsotg, HCFG);
5322 hr->haintmsk = dwc2_readl(hsotg, HAINTMSK);
5323 for (i = 0; i < hsotg->params.host_channels; ++i)
5324 hr->hcintmsk[i] = dwc2_readl(hsotg, HCINTMSK(i));
5326 hr->hprt0 = dwc2_read_hprt0(hsotg);
5327 hr->hfir = dwc2_readl(hsotg, HFIR);
5328 hr->hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
5339 * @hsotg: Programming view of the DWC_otg controller
5341 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
5346 dev_dbg(hsotg->dev, "%s\n", __func__);
5349 hr = &hsotg->hr_backup;
5351 dev_err(hsotg->dev, "%s: no host registers to restore\n",
5357 dwc2_writel(hsotg, hr->hcfg, HCFG);
5358 dwc2_writel(hsotg, hr->haintmsk, HAINTMSK);
5360 for (i = 0; i < hsotg->params.host_channels; ++i)
5361 dwc2_writel(hsotg, hr->hcintmsk[i], HCINTMSK(i));
5363 dwc2_writel(hsotg, hr->hprt0, HPRT0);
5364 dwc2_writel(hsotg, hr->hfir, HFIR);
5365 dwc2_writel(hsotg, hr->hptxfsiz, HPTXFSIZ);
5366 hsotg->frame_number = 0;
5374 * @hsotg: Programming view of the DWC_otg controller
5376 int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
5385 dev_dbg(hsotg->dev, "Preparing host for hibernation\n");
5386 ret = dwc2_backup_global_registers(hsotg);
5388 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5392 ret = dwc2_backup_host_registers(hsotg);
5394 dev_err(hsotg->dev, "%s: failed to backup host registers\n",
5400 hprt0 = dwc2_readl(hsotg, HPRT0);
5403 dwc2_writel(hsotg, hprt0, HPRT0);
5406 if (dwc2_hsotg_wait_bit_set(hsotg, HPRT0, HPRT0_SUSP, 5000))
5407 dev_warn(hsotg->dev, "Suspend wasn't generated\n");
5413 spin_lock_irqsave(&hsotg->lock, flags);
5414 hsotg->lx_state = DWC2_L2;
5416 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
5420 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5422 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5425 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5427 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5431 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5433 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5436 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5438 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5443 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5445 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5449 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5453 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5457 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5459 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5463 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5465 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5467 hsotg->hibernated = 1;
5468 hsotg->bus_suspended = 1;
5469 dev_dbg(hsotg->dev, "Host hibernation completed\n");
5470 spin_unlock_irqrestore(&hsotg->lock, flags);
5477 * @hsotg: Programming view of the DWC_otg controller
5486 int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
5495 gr = &hsotg->gr_backup;
5496 hr = &hsotg->hr_backup;
5498 dev_dbg(hsotg->dev,
5502 dwc2_hib_restore_common(hsotg, rem_wakeup, 1);
5503 hsotg->hibernated = 0;
5513 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5516 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5518 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5522 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5523 dwc2_writel(hsotg, hr->hcfg, HCFG);
5526 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5528 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5535 dwc2_writel(hsotg, hprt0, HPRT0);
5544 dwc2_writel(hsotg, hprt0, HPRT0);
5549 dwc2_writel(hsotg, hprt0, HPRT0);
5552 dwc2_writel(hsotg, hprt0, HPRT0);
5557 dwc2_writel(hsotg, hprt0, HPRT0);
5560 hprt0 = dwc2_readl(hsotg, HPRT0);
5564 dwc2_writel(hsotg, hprt0, HPRT0);
5566 hprt0 = dwc2_readl(hsotg, HPRT0);
5569 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5572 ret = dwc2_restore_global_registers(hsotg);
5574 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5580 ret = dwc2_restore_host_registers(hsotg);
5582 dev_err(hsotg->dev, "%s: failed to restore host registers\n",
5588 dwc2_hcd_rem_wakeup(hsotg);
5594 hsotg->flags.b.port_connect_status_change = 1;
5597 hsotg->hibernated = 0;
5598 hsotg->bus_suspended = 0;
5599 hsotg->lx_state = DWC2_L0;
5600 dev_dbg(hsotg->dev, "Host hibernation restore complete\n");