Lines Matching refs:hsotg
52 static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
54 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset);
57 static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
59 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset);
62 static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
66 return hsotg->eps_in[ep_index];
68 return hsotg->eps_out[ep_index];
72 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
76 * @hsotg: The driver state.
93 static inline bool using_dma(struct dwc2_hsotg *hsotg)
95 return hsotg->params.g_dma;
100 * @hsotg: The driver state.
104 static inline bool using_desc_dma(struct dwc2_hsotg *hsotg)
106 return hsotg->params.g_dma_desc;
118 struct dwc2_hsotg *hsotg = hs_ep->parent;
121 if (hsotg->gadget.speed != USB_SPEED_HIGH)
145 struct dwc2_hsotg *hsotg = hs_ep->parent;
148 if (hsotg->gadget.speed != USB_SPEED_HIGH)
159 * @hsotg: The device state
162 static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
164 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
170 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
171 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
177 * @hsotg: The device state
180 static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
182 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
188 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
193 * @hsotg: The device state
201 static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
213 daint = dwc2_readl(hsotg, DAINTMSK);
218 dwc2_writel(hsotg, daint, DAINTMSK);
225 * @hsotg: Programming view of the DWC_otg controller
227 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
229 if (hsotg->hw_params.en_multiple_tx_fifo)
231 return hsotg->hw_params.num_dev_in_eps;
234 return hsotg->hw_params.num_dev_perio_in_ep;
241 * @hsotg: Programming view of the DWC_otg controller
243 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
249 np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size,
250 hsotg->params.g_np_tx_fifo_size);
253 tx_addr_max = hsotg->hw_params.total_fifo_size;
255 addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size;
265 * @hsotg: Programming view of the DWC_otg controller
268 static void dwc2_gadget_wkup_alert_handler(struct dwc2_hsotg *hsotg)
273 gintsts2 = dwc2_readl(hsotg, GINTSTS2);
274 gintmsk2 = dwc2_readl(hsotg, GINTMSK2);
278 dev_dbg(hsotg->dev, "%s: Wkup_Alert_Int\n", __func__);
279 dwc2_set_bit(hsotg, GINTSTS2, GINTSTS2_WKUP_ALERT_INT);
280 dwc2_set_bit(hsotg, DCTL, DCTL_RMTWKUPSIG);
288 * @hsotg: Programming view of the DWC_otg controller
290 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
295 tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg);
297 tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
307 * @hsotg: The device instance.
309 static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
316 u32 *txfsz = hsotg->params.g_tx_fifo_size;
319 WARN_ON(hsotg->fifo_map);
320 hsotg->fifo_map = 0;
323 dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ);
324 dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size <<
326 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
337 addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;
349 WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,
353 dwc2_writel(hsotg, val, DPTXFSIZN(ep));
354 val = dwc2_readl(hsotg, DPTXFSIZN(ep));
357 dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size |
365 dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
371 val = dwc2_readl(hsotg, GRSTCTL);
377 dev_err(hsotg->dev,
386 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
424 * @hsotg: The device state.
431 static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
437 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->map_dir);
443 * @hsotg: The device state.
448 static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg)
450 hsotg->setup_desc[0] =
451 dmam_alloc_coherent(hsotg->dev,
453 &hsotg->setup_desc_dma[0],
455 if (!hsotg->setup_desc[0])
458 hsotg->setup_desc[1] =
459 dmam_alloc_coherent(hsotg->dev,
461 &hsotg->setup_desc_dma[1],
463 if (!hsotg->setup_desc[1])
466 hsotg->ctrl_in_desc =
467 dmam_alloc_coherent(hsotg->dev,
469 &hsotg->ctrl_in_desc_dma,
471 if (!hsotg->ctrl_in_desc)
474 hsotg->ctrl_out_desc =
475 dmam_alloc_coherent(hsotg->dev,
477 &hsotg->ctrl_out_desc_dma,
479 if (!hsotg->ctrl_out_desc)
490 * @hsotg: The controller state.
504 static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
509 u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS);
523 if (periodic && !hsotg->dedicated_fifos) {
524 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
540 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
544 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
553 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
557 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
561 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
564 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
565 can_write = dwc2_readl(hsotg,
572 dev_dbg(hsotg->dev,
576 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
586 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
606 if (!hsotg->dedicated_fifos)
607 dwc2_hsotg_en_gsint(hsotg,
635 if (!hsotg->dedicated_fifos)
636 dwc2_hsotg_en_gsint(hsotg,
641 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
656 dwc2_writel_rep(hsotg, EPFIFO(hs_ep->index), data, to_write);
702 * @hsotg: The device instance
706 static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
710 dsts = dwc2_readl(hsotg, DSTS);
914 struct dwc2_hsotg *hsotg = hs_ep->parent;
927 dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__);
935 dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n",
983 struct dwc2_hsotg *hsotg = hs_ep->parent;
995 dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__);
1026 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1028 ctrl = dwc2_readl(hsotg, depctl);
1030 dwc2_writel(hsotg, ctrl, depctl);
1034 static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1041 * @hsotg: The controller state.
1049 static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
1068 dev_err(hsotg->dev, "%s: active request\n", __func__);
1072 dev_err(hsotg->dev,
1083 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
1084 __func__, dwc2_readl(hsotg, epctrl_reg), index,
1088 ctrl = dwc2_readl(hsotg, epctrl_reg);
1091 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
1096 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
1099 if (!using_desc_dma(hsotg))
1107 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
1144 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
1150 if (using_desc_dma(hsotg)) {
1170 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1172 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
1176 dwc2_writel(hsotg, epsize, epsize_reg);
1178 if (using_dma(hsotg) && !continuing && (length != 0)) {
1184 dwc2_writel(hsotg, ureq->dma, dma_reg);
1186 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1203 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA);
1210 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
1213 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
1216 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1217 dwc2_writel(hsotg, ctrl, epctrl_reg);
1227 if (dir_in && !using_dma(hsotg)) {
1231 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1240 if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA))
1241 dev_dbg(hsotg->dev,
1243 index, dwc2_readl(hsotg, epctrl_reg));
1245 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
1246 __func__, dwc2_readl(hsotg, epctrl_reg));
1249 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
1254 * @hsotg: The device state.
1264 static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
1271 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
1278 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
1284 static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
1291 if (!using_dma(hsotg) || !((long)req_buf & 3))
1296 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
1302 dev_err(hsotg->dev,
1317 dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
1322 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
1325 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
1349 struct dwc2_hsotg *hsotg = hs_ep->parent;
1351 u32 current_frame = hsotg->frame_number;
1355 if (hsotg->gadget.speed != USB_SPEED_HIGH)
1370 * @hsotg: The driver state
1376 static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
1379 switch (hsotg->ep0_state) {
1382 hs_ep->desc_list = hsotg->setup_desc[0];
1383 hs_ep->desc_list_dma = hsotg->setup_desc_dma[0];
1387 hs_ep->desc_list = hsotg->ctrl_in_desc;
1388 hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma;
1391 hs_ep->desc_list = hsotg->ctrl_out_desc;
1392 hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma;
1395 dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n",
1396 hsotg->ep0_state);
1558 struct dwc2_hsotg *hsotg = hs_ep->parent;
1560 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
1567 * @hsotg: The driver state.
1573 static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
1582 if (idx > hsotg->num_of_eps)
1585 return index_to_ep(hsotg, idx, dir);
1590 * @hsotg: The driver state.
1594 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1596 int dctl = dwc2_readl(hsotg, DCTL);
1610 dwc2_writel(hsotg, dctl, DCTL);
1616 * @hsotg: The device state
1624 static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
1632 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1635 hsotg->ep0_reply = req;
1637 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1641 req->buf = hsotg->ep0_buff;
1655 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1664 * @hsotg: The device state
1667 static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
1670 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1676 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1679 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1685 status = hsotg->gadget.is_selfpowered <<
1687 status |= hsotg->remote_wakeup_allowed <<
1698 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1712 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1714 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1745 struct dwc2_hsotg *hsotg = hs_ep->parent;
1751 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1758 dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
1761 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1768 * @hsotg: The device state
1771 static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1774 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1784 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1796 hsotg->remote_wakeup_allowed = 1;
1798 hsotg->remote_wakeup_allowed = 0;
1807 hsotg->test_mode = wIndex >> 8;
1813 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1815 dev_err(hsotg->dev,
1822 ep = ep_from_windex(hsotg, wIndex);
1824 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1835 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1837 dev_err(hsotg->dev,
1857 spin_unlock(&hsotg->lock);
1860 spin_lock(&hsotg->lock);
1881 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1885 * @hsotg: The device state
1889 static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1891 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1895 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1903 ctrl = dwc2_readl(hsotg, reg);
1906 dwc2_writel(hsotg, ctrl, reg);
1908 dev_dbg(hsotg->dev,
1910 ctrl, reg, dwc2_readl(hsotg, reg));
1916 dwc2_hsotg_enqueue_setup(hsotg);
1921 * @hsotg: The device state
1928 static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1931 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1935 dev_dbg(hsotg->dev,
1942 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1945 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1948 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1954 hsotg->connected = 1;
1955 dcfg = dwc2_readl(hsotg, DCFG);
1959 dwc2_writel(hsotg, dcfg, DCFG);
1961 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1963 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1967 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1972 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1979 if (ret == 0 && hsotg->driver) {
1980 spin_unlock(&hsotg->lock);
1981 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1982 spin_lock(&hsotg->lock);
1984 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1987 hsotg->delayed_status = false;
1989 hsotg->delayed_status = true;
1997 dwc2_hsotg_stall_ep0(hsotg);
2012 struct dwc2_hsotg *hsotg = hs_ep->parent;
2015 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
2019 spin_lock(&hsotg->lock);
2021 dwc2_hsotg_enqueue_setup(hsotg);
2023 dwc2_hsotg_process_control(hsotg, req->buf);
2024 spin_unlock(&hsotg->lock);
2029 * @hsotg: The device state.
2034 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
2036 struct usb_request *req = hsotg->ctrl_req;
2040 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
2044 req->buf = hsotg->ctrl_buff;
2048 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
2052 hsotg->eps_out[0]->dir_in = 0;
2053 hsotg->eps_out[0]->send_zlp = 0;
2054 hsotg->ep0_state = DWC2_EP0_SETUP;
2056 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
2058 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
2066 static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
2075 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
2078 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
2080 if (using_desc_dma(hsotg)) {
2085 dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
2089 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2094 ctrl = dwc2_readl(hsotg, epctl_reg);
2098 dwc2_writel(hsotg, ctrl, epctl_reg);
2103 * @hsotg: The device state.
2114 static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
2120 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
2124 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
2135 if (using_dma(hsotg))
2136 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
2138 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
2149 spin_unlock(&hsotg->lock);
2151 spin_lock(&hsotg->lock);
2155 if (using_desc_dma(hsotg) && hs_ep->isochronous)
2179 struct dwc2_hsotg *hsotg = hs_ep->parent;
2193 dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__);
2218 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2238 struct dwc2_hsotg *hsotg = hs_ep->parent;
2241 dwc2_flush_rx_fifo(hsotg);
2242 dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0);
2251 * @hsotg: The device state.
2259 static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2261 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
2268 u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx));
2271 dev_dbg(hsotg->dev,
2277 (void)dwc2_readl(hsotg, EPFIFO(ep_idx));
2286 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
2307 dwc2_readl_rep(hsotg, EPFIFO(ep_idx),
2313 * @hsotg: The device instance
2323 static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
2326 hsotg->eps_out[0]->dir_in = dir_in;
2327 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
2329 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
2342 struct dwc2_hsotg *hsotg = hs_ep->parent;
2365 dev_err(hsotg->dev, "descriptor %d closed with %x\n",
2379 * @hsotg: The device instance
2386 static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2388 u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum));
2389 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
2396 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
2400 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
2401 dev_dbg(hsotg->dev, "zlp packet received\n");
2402 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2403 dwc2_hsotg_enqueue_setup(hsotg);
2407 if (using_desc_dma(hsotg))
2410 if (using_dma(hsotg)) {
2430 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2435 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
2445 if (!using_desc_dma(hsotg) && epnum == 0 &&
2446 hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2448 if (!hsotg->delayed_status)
2449 dwc2_hsotg_ep0_zlp(hsotg, true);
2453 if (!using_desc_dma(hsotg) && hs_ep->isochronous) {
2458 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
2463 * @hsotg: The device instance
2477 static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2479 u32 grxstsr = dwc2_readl(hsotg, GRXSTSP);
2482 WARN_ON(using_dma(hsotg));
2490 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
2495 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
2499 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
2500 dwc2_hsotg_read_frameno(hsotg));
2502 if (!using_dma(hsotg))
2503 dwc2_hsotg_handle_outdone(hsotg, epnum);
2507 dev_dbg(hsotg->dev,
2509 dwc2_hsotg_read_frameno(hsotg),
2510 dwc2_readl(hsotg, DOEPCTL(0)));
2516 if (hsotg->ep0_state == DWC2_EP0_SETUP)
2517 dwc2_hsotg_handle_outdone(hsotg, epnum);
2521 dwc2_hsotg_rx_data(hsotg, epnum, size);
2525 dev_dbg(hsotg->dev,
2527 dwc2_hsotg_read_frameno(hsotg),
2528 dwc2_readl(hsotg, DOEPCTL(0)));
2530 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
2532 dwc2_hsotg_rx_data(hsotg, epnum, size);
2536 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
2539 dwc2_hsotg_dump(hsotg);
2568 * @hsotg: The driver state.
2577 static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
2584 hs_ep = index_to_ep(hsotg, ep, dir_in);
2607 reg = dwc2_readl(hsotg, DIEPCTL(ep));
2610 dwc2_writel(hsotg, reg, DIEPCTL(ep));
2612 reg = dwc2_readl(hsotg, DOEPCTL(ep));
2615 dwc2_writel(hsotg, reg, DOEPCTL(ep));
2621 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
2626 * @hsotg: The driver state
2629 static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
2631 dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
2635 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100))
2636 dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n",
2642 * @hsotg: The driver state
2648 static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
2659 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
2665 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
2667 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
2675 * @hsotg: The device state.
2681 static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
2685 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
2689 dev_dbg(hsotg->dev, "XferCompl but no req\n");
2694 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
2695 dev_dbg(hsotg->dev, "zlp packet sent\n");
2703 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2704 if (hsotg->test_mode) {
2707 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
2709 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
2710 hsotg->test_mode);
2711 dwc2_hsotg_stall_ep0(hsotg);
2715 dwc2_hsotg_enqueue_setup(hsotg);
2728 if (using_desc_dma(hsotg)) {
2731 dev_err(hsotg->dev, "error parsing DDMA results %d\n",
2741 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
2745 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
2749 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
2750 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2757 if (!using_desc_dma(hsotg)) {
2758 dwc2_hsotg_program_zlp(hsotg, hs_ep);
2764 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
2766 dwc2_hsotg_ep0_zlp(hsotg, false);
2771 if (!using_desc_dma(hsotg) && hs_ep->isochronous) {
2776 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2781 * @hsotg: The device state.
2788 static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
2797 mask = dwc2_readl(hsotg, epmsk_reg);
2798 diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK);
2802 ints = dwc2_readl(hsotg, epint_reg);
2822 struct dwc2_hsotg *hsotg = hs_ep->parent;
2827 int dctl = dwc2_readl(hsotg, DCTL);
2829 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2832 int epctl = dwc2_readl(hsotg, epctl_reg);
2834 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2837 int dctl = dwc2_readl(hsotg, DCTL);
2840 dwc2_writel(hsotg, dctl, DCTL);
2846 dwc2_writel(hsotg, dctl, DCTL);
2854 dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n",
2864 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
2869 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2886 struct dwc2_hsotg *hsotg = ep->parent;
2893 if (using_desc_dma(hsotg)) {
2896 ep->target_frame = hsotg->frame_number;
2905 ep->target_frame = hsotg->frame_number;
2907 ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index));
2913 dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index));
2922 dwc2_hsotg_complete_request(hsotg, ep, hs_req, -ENODATA);
2927 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2935 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
2954 struct dwc2_hsotg *hsotg = hs_ep->parent;
2964 if (using_desc_dma(hsotg)) {
2965 hs_ep->target_frame = hsotg->frame_number;
2971 if (hsotg->params.service_interval) {
2988 hs_ep->target_frame = hsotg->frame_number;
2990 u32 ctrl = dwc2_readl(hsotg,
2997 dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index));
3001 if (using_desc_dma(hsotg))
3004 ctrl = dwc2_readl(hsotg, DIEPCTL(hs_ep->index));
3006 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
3008 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
3015 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA);
3020 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
3029 * @hsotg: The driver state
3035 static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
3038 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
3044 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
3047 dwc2_writel(hsotg, ints, epint_reg);
3050 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
3055 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
3068 if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in &&
3069 hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP))
3073 dev_dbg(hsotg->dev,
3075 __func__, dwc2_readl(hsotg, epctl_reg),
3076 dwc2_readl(hsotg, epsiz_reg));
3079 if (using_desc_dma(hsotg) && hs_ep->isochronous) {
3088 dwc2_hsotg_complete_in(hsotg, hs_ep);
3091 dwc2_hsotg_enqueue_setup(hsotg);
3092 } else if (using_dma(hsotg)) {
3098 dwc2_hsotg_handle_outdone(hsotg, idx);
3112 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
3115 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
3117 if (using_dma(hsotg) && idx == 0) {
3128 dwc2_hsotg_handle_outdone(hsotg, 0);
3133 dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
3136 if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
3138 if (using_desc_dma(hsotg)) {
3139 if (!hsotg->delayed_status)
3140 dwc2_hsotg_ep0_zlp(hsotg, true);
3149 dwc2_set_bit(hsotg, DIEPCTL(0),
3157 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
3160 dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__);
3168 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
3174 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
3179 if (hsotg->dedicated_fifos &&
3181 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
3183 if (!using_dma(hsotg))
3184 dwc2_hsotg_trytx(hsotg, hs_ep);
3191 * @hsotg: The device state.
3196 static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
3198 u32 dsts = dwc2_readl(hsotg, DSTS);
3207 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
3219 hsotg->gadget.speed = USB_SPEED_FULL;
3225 hsotg->gadget.speed = USB_SPEED_HIGH;
3231 hsotg->gadget.speed = USB_SPEED_LOW;
3241 dev_info(hsotg->dev, "new device is %s\n",
3242 usb_speed_string(hsotg->gadget.speed));
3252 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1);
3253 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0);
3254 for (i = 1; i < hsotg->num_of_eps; i++) {
3255 if (hsotg->eps_in[i])
3256 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3258 if (hsotg->eps_out[i])
3259 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3266 dwc2_hsotg_enqueue_setup(hsotg);
3268 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3269 dwc2_readl(hsotg, DIEPCTL0),
3270 dwc2_readl(hsotg, DOEPCTL0));
3275 * @hsotg: The device state.
3282 static void kill_all_requests(struct dwc2_hsotg *hsotg,
3293 dwc2_hsotg_complete_request(hsotg, ep, req, result);
3296 if (!hsotg->dedicated_fifos)
3298 size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
3300 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
3305 * @hsotg: The device state.
3311 void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
3315 if (!hsotg->connected)
3318 hsotg->connected = 0;
3319 hsotg->test_mode = 0;
3322 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3323 if (hsotg->eps_in[ep])
3324 kill_all_requests(hsotg, hsotg->eps_in[ep],
3326 if (hsotg->eps_out[ep])
3327 kill_all_requests(hsotg, hsotg->eps_out[ep],
3331 call_gadget(hsotg, disconnect);
3332 hsotg->lx_state = DWC2_L3;
3334 usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED);
3339 * @hsotg: The device state:
3342 static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
3348 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
3349 ep = index_to_ep(hsotg, epno, 1);
3361 ret = dwc2_hsotg_trytx(hsotg, ep);
3375 * @hsotg: The device state
3380 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3390 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
3393 if (dwc2_core_reset(hsotg, true))
3397 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
3398 if (hsotg->eps_in[ep])
3399 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3400 if (hsotg->eps_out[ep])
3401 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3411 usbcfg = dwc2_readl(hsotg, GUSBCFG);
3417 dwc2_writel(hsotg, usbcfg, GUSBCFG);
3419 dwc2_phy_init(hsotg, true);
3421 dwc2_hsotg_init_fifo(hsotg);
3424 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3428 switch (hsotg->params.speed) {
3433 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS)
3442 if (hsotg->params.ipg_isoc_en)
3445 dwc2_writel(hsotg, dcfg, DCFG);
3448 dwc2_writel(hsotg, 0xffffffff, GOTGINT);
3451 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
3459 if (!using_desc_dma(hsotg))
3462 if (!hsotg->params.external_id_pin_ctl)
3465 dwc2_writel(hsotg, intmsk, GINTMSK);
3467 if (using_dma(hsotg)) {
3468 dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
3469 hsotg->params.ahbcfg,
3473 if (using_desc_dma(hsotg))
3474 dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN);
3477 dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ?
3489 dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
3499 dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
3506 if (using_desc_dma(hsotg)) {
3507 dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK);
3508 dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK);
3512 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3513 dwc2_set_bit(hsotg, DCTL, DCTL_SERVICE_INTERVAL_SUPPORTED);
3515 dwc2_writel(hsotg, 0, DAINTMSK);
3517 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3518 dwc2_readl(hsotg, DIEPCTL0),
3519 dwc2_readl(hsotg, DOEPCTL0));
3522 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
3529 if (!using_dma(hsotg))
3530 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
3533 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
3534 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
3537 dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3539 dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3542 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL));
3550 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3553 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3559 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3566 dwc2_set_bit(hsotg, DCTL, val);
3569 dwc2_gadget_init_lpm(hsotg);
3572 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3573 dwc2_gadget_program_ref_clk(hsotg);
3578 hsotg->lx_state = DWC2_L0;
3580 dwc2_hsotg_enqueue_setup(hsotg);
3582 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3583 dwc2_readl(hsotg, DIEPCTL0),
3584 dwc2_readl(hsotg, DOEPCTL0));
3587 void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
3590 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3593 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
3596 if (!hsotg->role_sw || (dwc2_readl(hsotg, GOTGCTL) & GOTGCTL_BSESVLD))
3597 dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON);
3602 * @hsotg: The device state:
3613 static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3620 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
3622 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3624 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3625 hs_ep = hsotg->eps_in[idx];
3630 epctrl = dwc2_readl(hsotg, DIEPCTL(idx));
3635 dwc2_writel(hsotg, epctrl, DIEPCTL(idx));
3640 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS);
3645 * @hsotg: The device state:
3656 static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3665 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
3667 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3670 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3671 hs_ep = hsotg->eps_out[idx];
3676 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3680 gintmsk = dwc2_readl(hsotg, GINTMSK);
3682 dwc2_writel(hsotg, gintmsk, GINTMSK);
3684 gintsts = dwc2_readl(hsotg, GINTSTS);
3686 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3693 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS);
3703 struct dwc2_hsotg *hsotg = pw;
3708 if (!dwc2_is_device_mode(hsotg))
3711 spin_lock(&hsotg->lock);
3713 gintsts = dwc2_readl(hsotg, GINTSTS);
3714 gintmsk = dwc2_readl(hsotg, GINTMSK);
3716 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
3722 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
3724 dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS);
3727 if (hsotg->lx_state == DWC2_L2) {
3728 dwc2_exit_partial_power_down(hsotg, true);
3729 hsotg->lx_state = DWC2_L0;
3734 u32 usb_status = dwc2_readl(hsotg, GOTGCTL);
3735 u32 connected = hsotg->connected;
3737 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
3738 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
3739 dwc2_readl(hsotg, GNPTXSTS));
3741 dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS);
3744 dwc2_hsotg_disconnect(hsotg);
3747 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
3750 dwc2_hsotg_core_init_disconnected(hsotg, true);
3754 dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS);
3756 dwc2_hsotg_irq_enumdone(hsotg);
3760 u32 daint = dwc2_readl(hsotg, DAINT);
3761 u32 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3769 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
3771 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
3774 dwc2_hsotg_epint(hsotg, ep, 0);
3777 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
3780 dwc2_hsotg_epint(hsotg, ep, 1);
3787 dev_dbg(hsotg->dev, "NPTxFEmp\n");
3795 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
3796 dwc2_hsotg_irq_fifoempty(hsotg, false);
3800 dev_dbg(hsotg->dev, "PTxFEmp\n");
3804 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
3805 dwc2_hsotg_irq_fifoempty(hsotg, true);
3815 dwc2_hsotg_handle_rx(hsotg);
3819 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
3820 dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS);
3836 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3839 gintmsk = dwc2_readl(hsotg, GINTMSK);
3841 dwc2_writel(hsotg, gintmsk, GINTMSK);
3843 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
3844 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3845 hs_ep = hsotg->eps_out[idx];
3850 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3856 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3866 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3874 dev_info(hsotg->dev, "GINNakEff triggered\n");
3876 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3878 dwc2_hsotg_dump(hsotg);
3882 dwc2_gadget_handle_incomplete_isoc_in(hsotg);
3885 dwc2_gadget_handle_incomplete_isoc_out(hsotg);
3896 if (hsotg->params.service_interval)
3897 dwc2_gadget_wkup_alert_handler(hsotg);
3899 spin_unlock(&hsotg->lock);
3904 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3915 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
3919 if (hsotg->dedicated_fifos || hs_ep->periodic) {
3920 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK);
3922 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3924 dev_warn(hsotg->dev,
3928 dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK);
3930 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3932 dev_warn(hsotg->dev,
3938 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_GOUTNAKEFF);
3940 if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF))
3941 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3943 if (!using_dma(hsotg)) {
3945 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3947 dev_warn(hsotg->dev, "%s: timeout GINTSTS.RXFLVL\n",
3954 dwc2_readl(hsotg, GRXSTSP);
3959 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3961 dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
3966 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
3969 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
3970 dev_warn(hsotg->dev,
3974 dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD);
3979 if (hsotg->dedicated_fifos || hs_ep->periodic)
3985 dwc2_flush_tx_fifo(hsotg, fifo_index);
3988 if (!hsotg->dedicated_fifos && !hs_ep->periodic)
3989 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3993 dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK);
4008 struct dwc2_hsotg *hsotg = hs_ep->parent;
4022 dev_dbg(hsotg->dev,
4029 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
4035 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
4044 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
4046 dev_err(hsotg->dev,
4052 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
4054 dev_err(hsotg->dev,
4062 epctrl = dwc2_readl(hsotg, epctrl_reg);
4064 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
4067 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC)
4073 if (using_desc_dma(hsotg) && !hs_ep->desc_list) {
4074 hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev,
4083 spin_lock_irqsave(&hsotg->lock, flags);
4095 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in);
4114 mask = dwc2_readl(hsotg, DIEPMSK);
4116 dwc2_writel(hsotg, mask, DIEPMSK);
4119 mask = dwc2_readl(hsotg, DOEPMSK);
4121 dwc2_writel(hsotg, mask, DOEPMSK);
4133 if (hsotg->gadget.speed == USB_SPEED_HIGH)
4148 if (dir_in && hsotg->dedicated_fifos) {
4149 unsigned fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
4155 if (hsotg->fifo_map & (1 << i))
4157 val = dwc2_readl(hsotg, DPTXFSIZN(i));
4168 dev_err(hsotg->dev,
4174 hsotg->fifo_map |= 1 << fifo_index;
4190 if (hsotg->gadget.speed == USB_SPEED_FULL &&
4196 u32 gsnpsid = dwc2_readl(hsotg, GSNPSID);
4205 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
4208 dwc2_writel(hsotg, epctrl, epctrl_reg);
4209 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
4210 __func__, dwc2_readl(hsotg, epctrl_reg));
4213 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
4216 spin_unlock_irqrestore(&hsotg->lock, flags);
4219 if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
4220 dmam_free_coherent(hsotg->dev, desc_num *
4236 struct dwc2_hsotg *hsotg = hs_ep->parent;
4242 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
4244 if (ep == &hsotg->eps_out[0]->ep) {
4245 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
4249 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4250 dev_err(hsotg->dev, "%s: called in host mode?\n", __func__);
4256 ctrl = dwc2_readl(hsotg, epctrl_reg);
4259 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
4265 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
4266 dwc2_writel(hsotg, ctrl, epctrl_reg);
4269 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
4272 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
4274 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
4284 struct dwc2_hsotg *hsotg = hs_ep->parent;
4288 spin_lock_irqsave(&hsotg->lock, flags);
4290 spin_unlock_irqrestore(&hsotg->lock, flags);
4456 * @hsotg: The driver state
4458 static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4462 dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
4466 dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
4470 dwc2_writel(hsotg, 0, DAINTMSK);
4473 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
4477 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4478 dwc2_readl(hsotg, GRXFSIZ),
4479 dwc2_readl(hsotg, GNPTXFSIZ));
4481 dwc2_hsotg_init_fifo(hsotg);
4483 if (using_dma(hsotg))
4484 dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN);
4498 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4502 if (!hsotg) {
4508 dev_err(hsotg->dev, "%s: no driver\n", __func__);
4513 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
4516 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
4520 WARN_ON(hsotg->driver);
4522 hsotg->driver = driver;
4523 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
4524 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4526 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
4527 ret = dwc2_lowlevel_hw_enable(hsotg);
4532 if (!IS_ERR_OR_NULL(hsotg->uphy))
4533 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
4535 spin_lock_irqsave(&hsotg->lock, flags);
4536 if (dwc2_hw_is_device(hsotg)) {
4537 dwc2_hsotg_init(hsotg);
4538 dwc2_hsotg_core_init_disconnected(hsotg, false);
4541 hsotg->enabled = 0;
4542 spin_unlock_irqrestore(&hsotg->lock, flags);
4544 gadget->sg_supported = using_desc_dma(hsotg);
4545 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
4550 hsotg->driver = NULL;
4562 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4566 if (!hsotg)
4570 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
4571 if (hsotg->eps_in[ep])
4572 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
4573 if (hsotg->eps_out[ep])
4574 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
4577 spin_lock_irqsave(&hsotg->lock, flags);
4579 hsotg->driver = NULL;
4580 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4581 hsotg->enabled = 0;
4583 spin_unlock_irqrestore(&hsotg->lock, flags);
4585 if (!IS_ERR_OR_NULL(hsotg->uphy))
4586 otg_set_peripheral(hsotg->uphy->otg, NULL);
4588 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4589 dwc2_lowlevel_hw_disable(hsotg);
4615 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4618 spin_lock_irqsave(&hsotg->lock, flags);
4620 spin_unlock_irqrestore(&hsotg->lock, flags);
4634 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4637 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
4638 hsotg->op_state);
4641 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4642 hsotg->enabled = is_on;
4646 spin_lock_irqsave(&hsotg->lock, flags);
4648 hsotg->enabled = 1;
4649 dwc2_hsotg_core_init_disconnected(hsotg, false);
4651 dwc2_enable_acg(hsotg);
4652 dwc2_hsotg_core_connect(hsotg);
4654 dwc2_hsotg_core_disconnect(hsotg);
4655 dwc2_hsotg_disconnect(hsotg);
4656 hsotg->enabled = 0;
4659 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4660 spin_unlock_irqrestore(&hsotg->lock, flags);
4667 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4670 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
4671 spin_lock_irqsave(&hsotg->lock, flags);
4677 if (hsotg->lx_state == DWC2_L2)
4678 dwc2_exit_partial_power_down(hsotg, false);
4681 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4683 dwc2_hsotg_core_init_disconnected(hsotg, false);
4684 if (hsotg->enabled) {
4686 dwc2_enable_acg(hsotg);
4687 dwc2_hsotg_core_connect(hsotg);
4690 dwc2_hsotg_core_disconnect(hsotg);
4691 dwc2_hsotg_disconnect(hsotg);
4694 spin_unlock_irqrestore(&hsotg->lock, flags);
4707 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4709 if (IS_ERR_OR_NULL(hsotg->uphy))
4711 return usb_phy_set_power(hsotg->uphy, mA);
4726 * @hsotg: The device state.
4735 static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
4759 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
4761 hs_ep->parent = hsotg;
4764 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW)
4774 if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) {
4791 if (using_dma(hsotg)) {
4795 dwc2_writel(hsotg, next, DIEPCTL(epnum));
4797 dwc2_writel(hsotg, next, DOEPCTL(epnum));
4803 * @hsotg: Programming view of the DWC_otg controller
4807 static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
4815 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
4818 hsotg->num_of_eps++;
4820 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev,
4823 if (!hsotg->eps_in[0])
4826 hsotg->eps_out[0] = hsotg->eps_in[0];
4828 cfg = hsotg->hw_params.dev_ep_dirs;
4829 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
4833 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
4835 if (!hsotg->eps_in[i])
4840 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
4842 if (!hsotg->eps_out[i])
4847 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
4848 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
4850 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
4851 hsotg->num_of_eps,
4852 hsotg->dedicated_fifos ? "dedicated" : "shared",
4853 hsotg->fifo_mem);
4859 * @hsotg: Programming view of the DWC_otg controller
4862 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4865 struct device *dev = hsotg->dev;
4870 dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL),
4871 dwc2_readl(hsotg, DIEPMSK));
4874 dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1));
4877 dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ));
4881 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
4882 val = dwc2_readl(hsotg, DPTXFSIZN(idx));
4888 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
4891 dwc2_readl(hsotg, DIEPCTL(idx)),
4892 dwc2_readl(hsotg, DIEPTSIZ(idx)),
4893 dwc2_readl(hsotg, DIEPDMA(idx)));
4895 val = dwc2_readl(hsotg, DOEPCTL(idx));
4898 idx, dwc2_readl(hsotg, DOEPCTL(idx)),
4899 dwc2_readl(hsotg, DOEPTSIZ(idx)),
4900 dwc2_readl(hsotg, DOEPDMA(idx)));
4904 dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE));
4910 * @hsotg: Programming view of the DWC_otg controller
4913 int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
4915 struct device *dev = hsotg->dev;
4921 hsotg->params.g_np_tx_fifo_size);
4922 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size);
4924 hsotg->gadget.max_speed = USB_SPEED_HIGH;
4925 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
4926 hsotg->gadget.name = dev_name(dev);
4927 hsotg->remote_wakeup_allowed = 0;
4929 if (hsotg->params.lpm)
4930 hsotg->gadget.lpm_capable = true;
4932 if (hsotg->dr_mode == USB_DR_MODE_OTG)
4933 hsotg->gadget.is_otg = 1;
4934 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4935 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4937 ret = dwc2_hsotg_hw_cfg(hsotg);
4939 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
4943 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
4945 if (!hsotg->ctrl_buff)
4948 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
4950 if (!hsotg->ep0_buff)
4953 if (using_desc_dma(hsotg)) {
4954 ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg);
4959 ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq,
4960 IRQF_SHARED, dev_name(hsotg->dev), hsotg);
4966 /* hsotg->num_of_eps holds number of EPs other than ep0 */
4968 if (hsotg->num_of_eps == 0) {
4975 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
4976 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
4980 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
4982 if (!hsotg->ctrl_req) {
4988 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
4989 if (hsotg->eps_in[epnum])
4990 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
4992 if (hsotg->eps_out[epnum])
4993 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
4997 dwc2_hsotg_dump(hsotg);
5003 * dwc2_hsotg_remove - remove function for hsotg driver
5004 * @hsotg: Programming view of the DWC_otg controller
5007 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
5009 usb_del_gadget_udc(&hsotg->gadget);
5010 dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req);
5015 int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
5019 if (hsotg->lx_state != DWC2_L0)
5022 if (hsotg->driver) {
5025 dev_info(hsotg->dev, "suspending usb gadget %s\n",
5026 hsotg->driver->driver.name);
5028 spin_lock_irqsave(&hsotg->lock, flags);
5029 if (hsotg->enabled)
5030 dwc2_hsotg_core_disconnect(hsotg);
5031 dwc2_hsotg_disconnect(hsotg);
5032 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
5033 spin_unlock_irqrestore(&hsotg->lock, flags);
5035 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
5036 if (hsotg->eps_in[ep])
5037 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
5038 if (hsotg->eps_out[ep])
5039 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
5046 int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
5050 if (hsotg->lx_state == DWC2_L2)
5053 if (hsotg->driver) {
5054 dev_info(hsotg->dev, "resuming usb gadget %s\n",
5055 hsotg->driver->driver.name);
5057 spin_lock_irqsave(&hsotg->lock, flags);
5058 dwc2_hsotg_core_init_disconnected(hsotg, false);
5059 if (hsotg->enabled) {
5061 dwc2_enable_acg(hsotg);
5062 dwc2_hsotg_core_connect(hsotg);
5064 spin_unlock_irqrestore(&hsotg->lock, flags);
5075 * @hsotg: Programming view of the DWC_otg controller
5077 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
5082 dev_dbg(hsotg->dev, "%s\n", __func__);
5085 dr = &hsotg->dr_backup;
5087 dr->dcfg = dwc2_readl(hsotg, DCFG);
5088 dr->dctl = dwc2_readl(hsotg, DCTL);
5089 dr->daintmsk = dwc2_readl(hsotg, DAINTMSK);
5090 dr->diepmsk = dwc2_readl(hsotg, DIEPMSK);
5091 dr->doepmsk = dwc2_readl(hsotg, DOEPMSK);
5093 for (i = 0; i < hsotg->num_of_eps; i++) {
5095 dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i));
5103 dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i));
5104 dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i));
5107 dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i));
5115 dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i));
5116 dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i));
5117 dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i));
5128 * @hsotg: Programming view of the DWC_otg controller
5133 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
5138 dev_dbg(hsotg->dev, "%s\n", __func__);
5141 dr = &hsotg->dr_backup;
5143 dev_err(hsotg->dev, "%s: no device registers to restore\n",
5150 dwc2_writel(hsotg, dr->dctl, DCTL);
5152 dwc2_writel(hsotg, dr->daintmsk, DAINTMSK);
5153 dwc2_writel(hsotg, dr->diepmsk, DIEPMSK);
5154 dwc2_writel(hsotg, dr->doepmsk, DOEPMSK);
5156 for (i = 0; i < hsotg->num_of_eps; i++) {
5158 dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i));
5159 dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i));
5160 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5166 if (hsotg->params.g_dma_desc &&
5168 dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma;
5169 dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i));
5170 dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i));
5172 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5178 if (hsotg->params.g_dma_desc &&
5180 dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma;
5181 dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i));
5182 dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i));
5191 * @hsotg: Programming view of DWC_otg controller
5194 void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg)
5198 if (!hsotg->params.lpm)
5202 val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0;
5203 val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0;
5204 val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT;
5205 val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0;
5208 dwc2_writel(hsotg, val, GLPMCFG);
5209 dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG));
5212 if (hsotg->params.service_interval)
5213 dwc2_set_bit(hsotg, GINTMSK2, GINTMSK2_WKUP_ALERT_INT_MSK);
5219 * @hsotg: Programming view of DWC_otg controller
5222 void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg)
5227 val |= hsotg->params.ref_clk_per << GREFCLK_REFCLKPER_SHIFT;
5228 val |= hsotg->params.sof_cnt_wkup_alert <<
5231 dwc2_writel(hsotg, val, GREFCLK);
5232 dev_dbg(hsotg->dev, "GREFCLK=0x%08x\n", dwc2_readl(hsotg, GREFCLK));
5238 * @hsotg: Programming view of the DWC_otg controller
5242 int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
5248 hsotg->lx_state = DWC2_L2;
5249 dev_dbg(hsotg->dev, "Start of hibernation completed\n");
5250 ret = dwc2_backup_global_registers(hsotg);
5252 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5256 ret = dwc2_backup_device_registers(hsotg);
5258 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
5265 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5269 hsotg->hibernated = 1;
5272 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5274 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5278 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5282 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5286 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5288 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5292 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5294 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5298 hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN);
5299 dev_dbg(hsotg->dev, "Hibernation completed\n");
5309 * @hsotg: Programming view of the DWC_otg controller
5315 int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
5325 gr = &hsotg->gr_backup;
5326 dr = &hsotg->dr_backup;
5328 if (!hsotg->hibernated) {
5329 dev_dbg(hsotg->dev, "Already exited from Hibernation\n");
5332 dev_dbg(hsotg->dev,
5336 dwc2_hib_restore_common(hsotg, rem_wakeup, 0);
5340 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5344 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5346 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5350 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5352 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5356 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5357 dwc2_writel(hsotg, dr->dcfg, DCFG);
5358 dwc2_writel(hsotg, dr->dctl, DCTL);
5361 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5363 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5368 dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL);
5372 dctl = dwc2_readl(hsotg, DCTL);
5374 dwc2_writel(hsotg, dctl, DCTL);
5379 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5382 ret = dwc2_restore_global_registers(hsotg);
5384 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5390 ret = dwc2_restore_device_registers(hsotg, rem_wakeup);
5392 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5399 dctl = dwc2_readl(hsotg, DCTL);
5401 dwc2_writel(hsotg, dctl, DCTL);
5404 hsotg->hibernated = 0;
5405 hsotg->lx_state = DWC2_L0;
5406 dev_dbg(hsotg->dev, "Hibernation recovery completes here\n");