Lines Matching refs:val

167 	u32 val = 0;
175 val = readl(usbmisc->base);
176 val &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PP_BIT);
177 val |= (MX25_EHCI_INTERFACE_DIFF_UNI & MX25_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
178 val |= (MX25_OTG_PM_BIT | MX25_OTG_OCPOL_BIT);
185 val &= ~MX25_OTG_OCPOL_BIT;
187 writel(val, usbmisc->base);
190 val = readl(usbmisc->base);
191 val &= ~(MX25_H1_SIC_MASK | MX25_H1_PP_BIT | MX25_H1_IPPUE_UP_BIT);
192 val |= (MX25_EHCI_INTERFACE_SINGLE_UNI & MX25_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
193 val |= (MX25_H1_PM_BIT | MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT |
201 val &= ~MX25_H1_OCPOL_BIT;
203 writel(val, usbmisc->base);
217 u32 val;
227 val = readl(reg);
230 val |= MX25_BM_EXTERNAL_VBUS_DIVIDER;
232 val &= ~MX25_BM_EXTERNAL_VBUS_DIVIDER;
234 writel(val, reg);
245 u32 val;
249 val = MX27_OTG_PM_BIT;
252 val = MX27_H1_PM_BIT;
255 val = MX27_H2_PM_BIT;
263 val = readl(usbmisc->base) | val;
265 val = readl(usbmisc->base) & ~val;
266 writel(val, usbmisc->base);
277 u32 val = 0;
283 val = readl(usbmisc->base + MX53_USB_OTG_PHY_CTRL_1_OFFSET);
284 val &= ~MX53_USB_PHYCTRL1_PLLDIV_MASK;
285 val |= MX53_USB_PLL_DIV_24_MHZ;
286 writel(val, usbmisc->base + MX53_USB_OTG_PHY_CTRL_1_OFFSET);
294 val = readl(reg) | MX53_BM_OVER_CUR_DIS_OTG;
295 writel(val, reg);
301 val = readl(reg) | MX53_BM_OVER_CUR_DIS_H1;
302 writel(val, reg);
309 val = readl(reg) | MX53_USB_CTRL_1_UH2_ULPI_EN;
311 val &= ~MX53_USB_CTRL_1_H2_XCVR_CLK_SEL_MASK;
312 val |= MX53_USB_CTRL_1_H2_XCVR_CLK_SEL_ULPI;
313 writel(val, reg);
316 val = readl(reg) | MX53_USB_UHx_CTRL_WAKE_UP_EN
318 writel(val, reg);
323 val = readl(reg) |
325 writel(val, reg);
331 val = readl(reg) | MX53_BM_OVER_CUR_DIS_UHx;
332 writel(val, reg);
339 val = readl(reg) | MX53_USB_CTRL_1_UH3_ULPI_EN;
341 val &= ~MX53_USB_CTRL_1_H3_XCVR_CLK_SEL_MASK;
342 val |= MX53_USB_CTRL_1_H3_XCVR_CLK_SEL_ULPI;
343 writel(val, reg);
346 val = readl(reg) | MX53_USB_UHx_CTRL_WAKE_UP_EN
348 writel(val, reg);
354 val = readl(reg) |
356 writel(val, reg);
361 val = readl(reg) | MX53_BM_OVER_CUR_DIS_UHx;
362 writel(val, reg);
390 u32 val;
397 val = readl(usbmisc->base + data->index * 4);
399 val &= ~MX6_USB_OTG_WAKEUP_BITS;
400 val |= usbmisc_wakeup_setting(data);
402 if (val & MX6_BM_WAKEUP_INTR)
404 val &= ~MX6_USB_OTG_WAKEUP_BITS;
406 writel(val, usbmisc->base + data->index * 4);
491 u32 val;
502 val = readl(usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET + offset);
503 if (!(val & MX6_BM_HSIC_DEV_CONN))
504 writel(val | MX6_BM_HSIC_DEV_CONN,
515 u32 val;
526 val = readl(usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET + offset);
527 val |= MX6_BM_HSIC_EN | MX6_BM_HSIC_CLK_ON;
529 val |= MX6_BM_HSIC_CLK_ON;
531 val &= ~MX6_BM_HSIC_CLK_ON;
533 writel(val, usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET + offset);
545 u32 val;
553 val = readl(reg);
554 writel(val | MX6SX_USB_VBUS_WAKEUP_SOURCE_BVALID, reg);
559 val = readl(usbmisc->base + data->index * 4);
560 writel(val & ~MX6SX_BM_DPDM_WAKEUP_EN,
567 val = readl(usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET);
568 val |= MX6SX_BM_HSIC_AUTO_RESUME;
569 writel(val, usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET);
600 u32 val;
603 val = readl(usbmisc->base);
605 val &= ~MX6_USB_OTG_WAKEUP_BITS;
606 val |= usbmisc_wakeup_setting(data);
607 writel(val, usbmisc->base);
609 if (val & MX6_BM_WAKEUP_INTR)
611 writel(val & ~MX6_USB_OTG_WAKEUP_BITS, usbmisc->base);
688 int val;
693 val = readl(usbmisc->base + MX7D_USB_OTG_PHY_CFG2);
694 val &= ~MX7D_USB_OTG_PHY_CFG2_CHRG_VDATSRCENB0;
695 writel(val, usbmisc->base + MX7D_USB_OTG_PHY_CFG2);
703 val = readl(usbmisc->base + MX7D_USB_OTG_PHY_CFG2);
704 writel(val | MX7D_USB_OTG_PHY_CFG2_CHRG_VDATSRCENB0 |
718 val = readl(usbmisc->base + MX7D_USB_OTG_PHY_STATUS);
719 if (val & MX7D_USB_OTG_PHY_STATUS_CHRGDET) {
734 u32 val;
737 val = readl(usbmisc->base + MX7D_USB_OTG_PHY_CFG2);
738 val &= ~(MX7D_USB_OTG_PHY_CFG2_CHRG_DCDENB |
742 writel(val, usbmisc->base + MX7D_USB_OTG_PHY_CFG2);
745 val = readl(usbmisc->base + MX7D_USBNC_USB_CTRL2);
746 val &= ~MX7D_USBNC_USB_CTRL2_OPMODE_OVERRIDE_MASK;
747 writel(val, usbmisc->base + MX7D_USBNC_USB_CTRL2);
749 val = readl(usbmisc->base + MX7D_USBNC_USB_CTRL2);
750 writel(val & ~MX7D_USBNC_USB_CTRL2_OPMODE_OVERRIDE_EN,
759 u32 val;
764 val = readl(usbmisc->base + MX7D_USB_OTG_PHY_CFG2);
765 writel(val | MX7D_USB_OTG_PHY_CFG2_CHRG_DCDENB,
770 val = readl(usbmisc->base + MX7D_USB_OTG_PHY_STATUS);
771 if (!(val & MX7D_USB_OTG_PHY_STATUS_LINE_STATE0)) {
784 val = readl(usbmisc->base + MX7D_USB_OTG_PHY_CFG2);
785 writel(val & ~MX7D_USB_OTG_PHY_CFG2_CHRG_DCDENB,
803 u32 val;
807 val = readl(usbmisc->base + MX7D_USB_OTG_PHY_CFG2);
808 val &= ~MX7D_USB_OTG_PHY_CFG2_CHRG_CHRGSEL;
809 writel(val | MX7D_USB_OTG_PHY_CFG2_CHRG_VDATSRCENB0 |
818 val = readl(usbmisc->base + MX7D_USB_OTG_PHY_STATUS);
819 if (!(val & MX7D_USB_OTG_PHY_STATUS_CHRGDET)) {
840 u32 val;
844 val = readl(usbmisc->base + MX7D_USB_OTG_PHY_STATUS);
845 if (!(val & MX7D_USB_OTG_PHY_STATUS_VBUS_VLD)) {
855 val = readl(usbmisc->base + MX7D_USBNC_USB_CTRL2);
856 val &= ~MX7D_USBNC_USB_CTRL2_OPMODE_OVERRIDE_MASK;
857 val |= MX7D_USBNC_USB_CTRL2_OPMODE_NON_DRIVING;
858 writel(val, usbmisc->base + MX7D_USBNC_USB_CTRL2);
860 val = readl(usbmisc->base + MX7D_USBNC_USB_CTRL2);
861 writel(val | MX7D_USBNC_USB_CTRL2_OPMODE_OVERRIDE_EN,