Lines Matching refs:trb
186 struct cdns3_trb *trb)
188 u32 offset = (char *)trb - (char *)priv_ep->trb_pool;
260 * The last trb has zeroed cycle bit
316 * cdns3_ep_inc_trb - increment a trb index.
952 struct cdns3_trb *trb)
964 priv_ep->wa1_trb = trb;
991 struct cdns3_trb *trb;
1011 trb = priv_ep->trb_pool + priv_ep->enqueue;
1014 priv_req->trb = trb;
1022 trb->buffer = cpu_to_le32(TRB_BUFFER(trb_dma));
1025 trb->buffer = cpu_to_le32(TRB_BUFFER(request->sg[sg_idx].dma_address));
1031 trb->length = cpu_to_le32(TRB_BURST_LEN(16) | TRB_LEN(length));
1040 trb->length |= cpu_to_le32(TRB_TDL_SS_SIZE(tdl));
1044 trb->control = cpu_to_le32(control);
1046 trace_cdns3_prepare_trb(priv_ep, priv_req->trb);
1049 * Memory barrier - Cycle Bit must be set before trb->length and
1050 * trb->buffer fields.
1116 struct cdns3_trb *trb;
1150 trb = priv_ep->trb_pool + priv_ep->enqueue;
1152 priv_req->trb = trb;
1190 * Fill LINK TRBs for left trb space to simply software process logic.
1193 *trb = *link_trb;
1194 trace_cdns3_prepare_trb(priv_ep, trb);
1197 trb = priv_ep->trb_pool + priv_ep->enqueue;
1198 priv_req->trb = trb;
1209 togle_pcs = cdns3_wa1_update_guard(priv_ep, trb);
1211 /* set incorrect Cycle Bit for first trb*/
1213 trb->length = 0;
1220 trb->length = cpu_to_le32(TRB_TDL_SS_SIZE(td_size));
1234 trb->buffer = cpu_to_le32(TRB_BUFFER(sg_dma_address(s)));
1237 trb->buffer = cpu_to_le32(TRB_BUFFER(trb_dma));
1270 if (ALIGN_DOWN(trb->buffer, SZ_4K) !=
1271 ALIGN_DOWN(trb->buffer + length, SZ_4K))
1274 trb->length |= cpu_to_le32(TRB_BURST_LEN(trb_burst) |
1279 * first trb should be prepared as last to avoid processing
1294 trb->control = cpu_to_le32(control);
1296 priv_req->trb->control = cpu_to_le32(control);
1299 trb->control |= cpu_to_le32(TRB_ISP);
1302 trb->control |= cpu_to_le32(TRB_CHAIN);
1311 trb = priv_ep->trb_pool + priv_ep->enqueue;
1312 trb->length = 0;
1315 trb = priv_req->trb;
1321 trb->control |= cpu_to_le32(TRB_IOC | TRB_ISP);
1341 * Memory barrier - cycle bit must be set before other filds in trb.
1347 trb->control = trb->control ^ cpu_to_le32(1);
1356 trace_cdns3_prepare_trb(priv_ep, trb + i);
1357 if (trb + i == link_trb) {
1358 trb = priv_ep->trb_pool;
1366 trace_cdns3_prepare_trb(priv_ep, priv_req->trb);
1370 * Memory barrier - Cycle Bit must be set before trb->length and
1371 * trb->buffer fields.
1441 * cdns3_trb_handled - check whether trb has been handled by DMA
1483 struct cdns3_trb *trb;
1491 /* current trb doesn't belong to this request */
1509 trb = &priv_ep->trb_pool[priv_ep->dequeue];
1511 if ((le32_to_cpu(trb->control) & TRB_CYCLE) != priv_ep->ccs)
1547 struct cdns3_trb *trb;
1555 trb = priv_ep->trb_pool + priv_ep->dequeue;
1558 while (TRB_FIELD_TO_TYPE(le32_to_cpu(trb->control)) == TRB_LINK) {
1565 trace_cdns3_complete_trb(priv_ep, trb);
1567 trb = priv_ep->trb_pool + priv_ep->dequeue;
1581 trb = priv_ep->trb_pool + priv_ep->dequeue;
1582 trace_cdns3_complete_trb(priv_ep, trb);
1586 TRB_LEN(le32_to_cpu(trb->length));
1589 le32_to_cpu(trb->control) & TRB_SMM &&
1590 le32_to_cpu(trb->control) & TRB_CHAIN)
1617 trb = priv_ep->trb_pool;
1618 trace_cdns3_complete_trb(priv_ep, trb);
1620 if (trb != priv_req->trb)
1623 priv_req->trb, trb);
1625 request->actual += TRB_LEN(le32_to_cpu(trb->length));
2716 link_trb = priv_req->trb;
2725 if (priv_ep->wa1_trb == priv_req->trb)
2767 struct cdns3_trb *trb = NULL;
2777 trb = priv_req->trb;
2778 if (trb) {
2779 trb_tmp = *trb;
2780 trb->control = trb->control ^ cpu_to_le32(TRB_CYCLE);
2795 if (trb)
2796 *trb = trb_tmp;