Lines Matching defs:value
102 static inline void cdns_imx_writel(struct cdns_imx *data, u32 offset, u32 value)
104 writel(value, data->noncore + offset);
117 u32 value;
123 ret = readl_poll_timeout(data->noncore + USB3_SSPHY_STATUS, value,
124 (value & CLK_VALID_COMPARE_BITS) == CLK_VALID_COMPARE_BITS,
131 value = cdns_imx_readl(data, USB3_CORE_CTRL1);
132 value |= ALL_SW_RESET;
133 cdns_imx_writel(data, USB3_CORE_CTRL1, value);
136 value = cdns_imx_readl(data, USB3_CORE_CTRL1);
137 value = (value & ~MODE_STRAP_MASK) | OTG_MODE | OC_DISABLE;
138 cdns_imx_writel(data, USB3_CORE_CTRL1, value);
140 value = cdns_imx_readl(data, USB3_INT_REG);
141 value |= HOST_INT1_EN | DEV_INT_EN;
142 cdns_imx_writel(data, USB3_INT_REG, value);
144 value = cdns_imx_readl(data, USB3_CORE_CTRL1);
145 value &= ~ALL_SW_RESET;
146 cdns_imx_writel(data, USB3_CORE_CTRL1, value);
234 u32 value;
236 value = cdns_imx_readl(data, USB3_INT_REG);
238 value |= OTG_WAKEUP_EN | DEVU3_WAEKUP_EN;
240 value &= ~(OTG_WAKEUP_EN | DEVU3_WAEKUP_EN);
242 cdns_imx_writel(data, USB3_INT_REG, value);
253 u32 value;
261 value = readl(xhci_regs + XECP_PM_PMCSR);
262 value &= ~PS_MASK;
263 value |= PS_D1;
264 writel(value, xhci_regs + XECP_PM_PMCSR);
267 value = cdns_imx_readl(data, USB3_CORE_CTRL1);
268 value |= MDCTRL_CLK_SEL;
269 cdns_imx_writel(data, USB3_CORE_CTRL1, value);
272 value = cdns_imx_readl(data, USB3_CORE_STATUS);
273 ret = readl_poll_timeout(data->noncore + USB3_CORE_STATUS, value,
274 (value & MDCTRL_CLK_STATUS) == MDCTRL_CLK_STATUS,
280 value = cdns_imx_readl(data, USB3_INT_REG);
281 ret = readl_poll_timeout(data->noncore + USB3_INT_REG, value,
282 (value & LPM_CLK_REQ) != LPM_CLK_REQ,
288 value = cdns_imx_readl(data, USB3_SSPHY_STATUS);
289 ret = readl_poll_timeout(data->noncore + USB3_SSPHY_STATUS, value,
290 (value & PHY_REFCLK_REQ) != PHY_REFCLK_REQ,
300 value = readl(xhci_regs + XECP_PM_PMCSR);
301 value &= ~PS_MASK;
302 value |= PS_D0;
303 writel(value, xhci_regs + XECP_PM_PMCSR);
306 value = readl(xhci_regs + XECP_AUX_CTRL_REG1);
307 value &= ~CFG_RXDET_P3_EN;
308 writel(value, xhci_regs + XECP_AUX_CTRL_REG1);
311 value = cdns_imx_readl(data, USB3_CORE_CTRL1);
312 value &= ~MDCTRL_CLK_SEL;
313 cdns_imx_writel(data, USB3_CORE_CTRL1, value);
316 value = cdns_imx_readl(data, USB3_INT_REG);
317 ret = readl_poll_timeout(data->noncore + USB3_INT_REG, value,
318 (value & CLK_125_REQ) == CLK_125_REQ,
324 value = cdns_imx_readl(data, USB3_CORE_STATUS);
325 ret = readl_poll_timeout(data->noncore + USB3_CORE_STATUS, value,
326 (value & MDCTRL_CLK_STATUS) != MDCTRL_CLK_STATUS,
332 value = readl(otg_regs + OTGSTS);
333 ret = readl_poll_timeout(otg_regs + OTGSTS, value,
334 (value & OTG_NRDY) != OTG_NRDY,