Lines Matching refs:TXDMA
386 #define TXDMA 0x20
2205 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2206 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2207 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2357 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2358 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2359 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2376 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2379 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2963 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
2964 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4210 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4211 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4214 write_reg16(info, TXDMA + CDA,
4218 write_reg16(info, TXDMA + EDA,
4227 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4228 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4254 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4255 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4509 write_reg(info, TXDMA + DIR, 0);
4651 write_reg(info, TXDMA + DMR, 0x14);
4659 write_reg(info, TXDMA + CPB,