Lines Matching refs:DSR
288 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
374 #define DSR 0x90
1288 /* Wait for modem input (DCD,RI,DSR,CTS) change
1289 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1295 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1365 strcat(stat_buf, "|DSR");
2206 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2323 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2326 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2340 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2343 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2358 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2376 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2379 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2963 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4109 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4135 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4160 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4210 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4228 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4254 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4740 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
5478 /* called to periodically check the DSR/RI modem signal input status
5492 /* check for DSR/RI state change */