Lines Matching defs:clear
549 unsigned int set, unsigned int clear);
1493 /* set or clear transmit break condition
1494 * break_state -1=set break condition, 0=clear
2085 /* clear status bits */
2206 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2215 /* disable and clear tx interrupts */
2263 /* clear status bits */
2325 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2342 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2358 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2378 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2665 /* clear status wait queue because status changes */
2961 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
3196 unsigned int set, unsigned int clear)
3203 __FILE__,__LINE__,info->device_name, set, clear);
3209 if (clear & TIOCM_RTS)
3211 if (clear & TIOCM_DTR)
4160 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4228 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4261 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
4725 /* clear all serial signals except RTS and DTR */