Lines Matching defs:val
2212 unsigned short val = rd_reg16(info, TCR);
2213 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2214 wr_reg16(info, TCR, val); /* clear reset bit */
2701 unsigned short val = rd_reg16(info, SCR);
2702 if (!(val & IRQ_RXIDLE))
2703 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2788 unsigned short val;
2797 val = rd_reg16(info, TCR);
2799 val |= BIT7;
2801 val &= ~BIT7;
2802 wr_reg16(info, TCR, val);
3888 unsigned short val;
3891 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3892 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3893 wr_reg16(info, RCR, val); /* clear reset bit */
3908 unsigned short val;
3916 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3917 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3918 wr_reg16(info, RCR, val); /* clear reset bit */
3995 unsigned short val;
4002 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
4003 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
4041 unsigned short val;
4065 val = 0x4000;
4068 val |= BIT7;
4071 val |= BIT9;
4073 val |= BIT8;
4078 case 6: val |= BIT4; break;
4079 case 7: val |= BIT5; break;
4080 case 8: val |= BIT5 + BIT4; break;
4084 val |= BIT3;
4087 val |= BIT0;
4089 wr_reg16(info, TCR, val);
4108 val = 0x4000;
4111 val |= BIT9;
4113 val |= BIT8;
4118 case 6: val |= BIT4; break;
4119 case 7: val |= BIT5; break;
4120 case 8: val |= BIT5 + BIT4; break;
4124 val |= BIT0;
4126 wr_reg16(info, RCR, val);
4160 val = BIT15 + BIT14 + BIT0;
4166 val |= BIT3;
4172 wr_reg16(info, SCR, val);
4182 unsigned short val;
4208 val = BIT2;
4212 val |= BIT15 + BIT13;
4214 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4215 case MGSL_MODE_BISYNC: val |= BIT15; break;
4216 case MGSL_MODE_RAW: val |= BIT13; break;
4219 val |= BIT7;
4223 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4224 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4225 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4226 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4227 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4228 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4229 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4234 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4235 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4239 val |= BIT6;
4243 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4244 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4245 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4249 val |= BIT0;
4251 wr_reg16(info, TCR, val);
4257 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4258 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4259 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4260 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4261 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4262 default: val = 0x7e; break;
4264 wr_reg8(info, TPR, (unsigned char)val);
4283 val = 0;
4287 val |= BIT15 + BIT13;
4289 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4290 case MGSL_MODE_BISYNC: val |= BIT15; break;
4291 case MGSL_MODE_RAW: val |= BIT13; break;
4296 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4297 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4298 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4299 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4300 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4301 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4302 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4307 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4308 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4312 val |= BIT0;
4314 wr_reg16(info, RCR, val);
4323 val = 0;
4331 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4333 val |= BIT6; /* 010, txclk = BRG */
4336 val |= BIT7; /* 100, txclk = DPLL Input */
4338 val |= BIT5; /* 001, txclk = RXC Input */
4341 val |= BIT3; /* 010, rxclk = BRG */
4343 val |= BIT4; /* 100, rxclk = DPLL */
4345 val |= BIT2; /* 001, rxclk = TXC Input */
4348 val |= BIT1 + BIT0;
4350 wr_reg8(info, CCR, (unsigned char)val);
4359 val = BIT7; break;
4362 val = BIT7 + BIT6; break;
4363 default: val = BIT6; // NRZ encodings
4365 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4407 unsigned char val;
4427 val = (unsigned char)(info->idle_mode & 0xff);
4432 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4434 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4436 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4437 default: val = 0xff;
4441 wr_reg8(info, TIR, val);
4469 unsigned char val = 0;
4483 val |= BIT5; /* 0010 */
4486 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4489 val |= BIT6; /* 0100 */
4494 val |= BIT4;
4496 val |= BIT3;
4498 val |= BIT2;
4500 val |= BIT1;
4502 val |= BIT0;
4503 wr_reg8(info, VCR, val);
4511 unsigned char val = rd_reg8(info, VCR);
4513 val |= BIT3;
4515 val &= ~BIT3;
4517 val |= BIT2;
4519 val &= ~BIT2;
4520 wr_reg8(info, VCR, val);