Lines Matching defs:set
270 u32 max_frame_size; /* as set by device config */
1316 * set or clear transmit break condition
1317 * break_state -1=set break condition, 0=clear
1576 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
2179 * is set to index of first unsent buffer
2213 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2817 * set extended sync pattern (1 to 4 bytes) for extended sync mode
2843 * set extended control options
2872 * set general purpose IO pin state and direction
2876 * smask set bit indicates pin state to set
2878 * dmask set bit indicates pin direction to set
2978 * smask - set bit indicates watched pin
2981 * state. When 0 (no error) is returned, user_gpio->state is set to the
3003 /* ignore output pins identified by set IODR bit */
3115 * set modem control signals (DTR/RTS)
3117 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3118 * TIOCMSET = set/clear signal values
3122 unsigned int set, unsigned int clear)
3127 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3129 if (set & TIOCM_RTS)
3131 if (set & TIOCM_DTR)
3186 /* nonblock mode is set or port is not enabled */
3537 info->init_error = -1; /* assume error, set to 0 on successful init */
3813 /* set reset bit */
3826 /* set reset bit */
3856 /* set speed if available, otherwise use default */
3865 * set baud rate generator to specified rate
3892 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3917 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3934 /* set 1st descriptor address */
3986 /* set 1st descriptor address and start DMA */
4003 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
4403 * set transmit idle mode
4415 /* disable preamble, set idle size to 16 bits */
4420 /* preamble is disabled, set idle size to 8 bits */
4465 * set V.24 Control Register based on current configuration
4507 * set state of V24 control (output) signals
4843 * set EOF bit for last buffer of HDLC frame or
4852 /* set descriptor count for all but first buffer */
4863 /* set first buffer count to make new data visible to DMA controller */