Lines Matching defs:clear
1316 * set or clear transmit break condition
1317 * break_state -1=set break condition, 0=clear
2073 wr_reg16(info, SSR, status); /* clear pending */
2141 wr_reg32(info, RDCSR, status); /* clear pending */
2166 wr_reg32(info, TDCSR, status); /* clear pending */
2214 wr_reg16(info, TCR, val); /* clear reset bit */
2311 /* clear pending GPIO interrupt bits */
2382 /* clear status wait queue because status changes */
3117 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3118 * TIOCMSET = set/clear signal values
3122 unsigned int set, unsigned int clear)
3127 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3133 if (clear & TIOCM_RTS)
3135 if (clear & TIOCM_DTR)
3891 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3893 wr_reg16(info, RCR, val); /* clear reset bit */
3897 /* clear pending rx interrupts */
3912 /* clear pending rx overrun IRQ */
3916 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3918 wr_reg16(info, RCR, val); /* clear reset bit */
3978 /* clear tx idle and underrun status bits */
3983 /* clear tx idle status bit */
4002 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
4007 /* clear tx idle and underrun status bit */
4451 /* clear all serial signals except RTS and DTR */