Lines Matching refs:BIT8
501 #define RXSTATUS_SHORT_FRAME BIT8
502 #define RXSTATUS_CODE_VIOLATION BIT8
563 #define MISCSTATUS_DSR BIT8
586 #define SICR_DSR_INACTIVE BIT8
587 #define SICR_DSR (BIT9|BIT8)
1639 usc_OutDmaReg(info, CDIR, BIT8 | BIT0 );
4383 /* Note: must preserve state of BIT8 in DCAR */
4411 /* Note: must preserve state of BIT8 in DCAR */
4675 RegValue |= BIT9 | BIT8;
4677 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
4838 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
4842 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 | BIT8; break;
4889 info->mbre_bit = BIT8;
4890 outw( BIT8, info->io_base ); /* set Master Bus Enable (DCAR) */
4991 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 | BIT12; break;
4992 case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break;
4994 case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 | BIT8; break;
5919 if (usc_InReg( info, RCSR ) & (BIT8 | BIT4 | BIT3 | BIT1))
7110 if ( status & (BIT8 | BIT3 | BIT1) ) {