Lines Matching defs:bus
255 unsigned char bus; /* expansion bus number (zero based) */
722 * local bus address ranges.
1836 /* This disconnects the DMA request signal from the ISA bus */
1841 /* This disconnects the IRQ request signal to the ISA bus */
3611 * using bus master DMA. The pointers to the actual buffers are filled
4903 * <11..10> 00 Both Channels can use each bus grant
5003 * <15..8> 0x20 Maximum number of transfers per bus grant
5004 * <7..0> 0x00 Maximum number of clock cycles per bus grant
5007 /* don't limit bus occupancy on PCI adapter */
5614 * <2> 1 Use 16 Bit data bus
6141 * the DMA system controller and DMA bus masters deal with memory using
6812 /* This connects the IRQ request signal to the ISA bus */
7232 * the adapter local bus, which can starve the 16C32 by preventing
7233 * 16C32 bus master cycles.
7236 * control of the local bus after completing the current read
7241 * and will not release the bus. This causes DMA latency problems
7249 * of the local bus in a timely fasion.
7262 /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */