Lines Matching defs:Control
138 volatile u16 status; /* Control/status field */
340 #define CCR 0x06 /* Channel Control Register */
342 #define PCR 0x0a /* Port Control Register */
344 #define TMCR 0x0e /* Test mode Control Register */
345 #define CMCR 0x10 /* Clock mode Control Register */
348 #define IOCR 0x16 /* Input/Output Control Register */
349 #define ICR 0x18 /* Interrupt Control Register */
350 #define DCCR 0x1a /* Daisy Chain Control Register */
352 #define SICR 0x1e /* status Interrupt Control Register */
356 #define RICR 0x26 /* Receive Interrupt Control Register */
364 #define TICR 0x36 /* Transmit Interrupt Control Register */
375 #define DCR 0x06 /* DMA Control Register (shared) */
377 #define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
379 #define DICR 0x18 /* DMA Interrupt Control Register (shared) */
486 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
519 * Transmit Control/status Register (TCSR)
620 * Transmit status Bits in Transmit Control status Register (TCSR)
621 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
649 /* Transmit status Bits in Transmit Control status Register (TCSR) */
650 /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
4620 /* Receive Interrupt Control Register (RICR)
4686 /* Transmit Interrupt Control Register (TICR)
4730 /* Clock mode Control Register (CMCR)
4849 /* Channel Control/status Register (CCSR)
4892 /* DMA Control Register (DCR)
4936 * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
4949 /* DMA Interrupt Control Register (DICR)
4968 /* Channel Control Register (CCR)
4970 * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
5001 * Burst/Dwell Control Register
5031 /* Clock mode Control Register (CMCR)
5057 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5117 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5573 /* Set BIT30 of Misc Control Register */
5574 /* (Local Control Register 0x50) to force reset of USC. */
5634 /* Port Control Register (PCR)
5652 * Input/Output Control Register
5737 /* Receive Interrupt Control Register (RICR)
5796 /* Transmit Interrupt Control Register (TICR)
5819 /* Channel Control/status Register (CCSR)
5883 /* Channel Control Register (CCR)
5885 * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
6054 u16 Control;
6057 /* get the current value of the Port Control Register (PCR) */
6059 Control = usc_InReg( info, PCR );
6062 Control &= ~(BIT6);
6064 Control |= BIT6;
6067 Control &= ~(BIT4);
6069 Control |= BIT4;
6071 usc_OutReg( info, PCR, Control );
6088 * Clock mode Control Register (CMCR)
6122 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6159 * DMA. Control information is read from the buffer entries by the