Lines Matching refs:membase
231 while ((readl(port->membase + CDNS_UART_SR) &
234 rxbs_status = readl(port->membase + CDNS_UART_RXBS);
235 data = readl(port->membase + CDNS_UART_FIFO);
319 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
323 !(readl(port->membase + CDNS_UART_SR) &
332 port->membase + CDNS_UART_FIFO);
370 isrstatus = readl(port->membase + CDNS_UART_ISR);
371 writel(isrstatus, port->membase + CDNS_UART_ISR);
385 !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS))
474 mreg = readl(port->membase + CDNS_UART_MR);
479 writel(mreg, port->membase + CDNS_UART_MR);
480 writel(cd, port->membase + CDNS_UART_BAUDGEN);
481 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
528 ctrl_reg = readl(port->membase + CDNS_UART_CR);
530 writel(ctrl_reg, port->membase + CDNS_UART_CR);
555 ctrl_reg = readl(port->membase + CDNS_UART_CR);
557 writel(ctrl_reg, port->membase + CDNS_UART_CR);
559 while (readl(port->membase + CDNS_UART_CR) &
568 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
569 ctrl_reg = readl(port->membase + CDNS_UART_CR);
572 writel(ctrl_reg, port->membase + CDNS_UART_CR);
598 status = readl(port->membase + CDNS_UART_CR);
601 writel(status, port->membase + CDNS_UART_CR);
606 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
611 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
622 regval = readl(port->membase + CDNS_UART_CR);
625 writel(regval, port->membase + CDNS_UART_CR);
637 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
640 regval = readl(port->membase + CDNS_UART_CR);
642 writel(regval, port->membase + CDNS_UART_CR);
655 status = readl(port->membase + CDNS_UART_SR) &
673 status = readl(port->membase + CDNS_UART_CR);
677 port->membase + CDNS_UART_CR);
681 port->membase + CDNS_UART_CR);
704 ctrl_reg = readl(port->membase + CDNS_UART_CR);
706 writel(ctrl_reg, port->membase + CDNS_UART_CR);
725 ctrl_reg = readl(port->membase + CDNS_UART_CR);
727 writel(ctrl_reg, port->membase + CDNS_UART_CR);
729 while (readl(port->membase + CDNS_UART_CR) &
737 ctrl_reg = readl(port->membase + CDNS_UART_CR);
740 writel(ctrl_reg, port->membase + CDNS_UART_CR);
742 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
762 mode_reg = readl(port->membase + CDNS_UART_MR);
803 writel(cval, port->membase + CDNS_UART_MR);
805 cval = readl(port->membase + CDNS_UART_MODEMCR);
810 writel(cval, port->membase + CDNS_UART_MODEMCR);
835 port->membase + CDNS_UART_CR);
841 port->membase + CDNS_UART_CR);
843 while (readl(port->membase + CDNS_UART_CR) &
851 status = readl(port->membase + CDNS_UART_CR);
854 writel(status, port->membase + CDNS_UART_CR);
861 port->membase + CDNS_UART_MR);
867 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
873 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
876 writel(readl(port->membase + CDNS_UART_ISR),
877 port->membase + CDNS_UART_ISR);
891 port->membase + CDNS_UART_IER);
893 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
910 status = readl(port->membase + CDNS_UART_IMR);
911 writel(status, port->membase + CDNS_UART_IDR);
912 writel(0xffffffff, port->membase + CDNS_UART_ISR);
916 port->membase + CDNS_UART_CR);
972 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
973 if (!port->membase) {
991 iounmap(port->membase);
992 port->membase = NULL;
1021 val = readl(port->membase + CDNS_UART_MODEMSR);
1043 val = readl(port->membase + CDNS_UART_MODEMCR);
1044 mode_reg = readl(port->membase + CDNS_UART_MR);
1058 writel(val, port->membase + CDNS_UART_MODEMCR);
1059 writel(mode_reg, port->membase + CDNS_UART_MR);
1071 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
1074 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
1088 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1092 writel(c, port->membase + CDNS_UART_FIFO);
1095 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1149 while (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)
1151 writel(ch, port->membase + CDNS_UART_FIFO);
1167 if (!port->membase)
1172 port->membase + CDNS_UART_CR);
1188 writel(mr, port->membase + CDNS_UART_MR);
1189 writel(cd, port->membase + CDNS_UART_BAUDGEN);
1190 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
1228 imr = readl(port->membase + CDNS_UART_IMR);
1229 writel(imr, port->membase + CDNS_UART_IDR);
1235 ctrl = readl(port->membase + CDNS_UART_CR);
1238 writel(ctrl, port->membase + CDNS_UART_CR);
1245 writel(imr, port->membase + CDNS_UART_IER);
1268 if (!port->membase) {
1318 while (!(readl(port->membase + CDNS_UART_SR) &
1320 readl(port->membase + CDNS_UART_FIFO);
1322 writel(1, port->membase + CDNS_UART_RXWM);
1324 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1358 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1360 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1361 while (readl(port->membase + CDNS_UART_CR) &
1366 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1368 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1371 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1379 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1381 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);