Lines Matching defs:qe_port
218 static inline dma_addr_t cpu2qe_addr(void *addr, struct uart_qe_port *qe_port)
220 if (likely((addr >= qe_port->bd_virt)) &&
221 (addr < (qe_port->bd_virt + qe_port->bd_size)))
222 return qe_port->bd_dma_addr + (addr - qe_port->bd_virt);
236 static inline void *qe2cpu_addr(dma_addr_t addr, struct uart_qe_port *qe_port)
239 if (likely((addr >= qe_port->bd_dma_addr) &&
240 (addr < (qe_port->bd_dma_addr + qe_port->bd_size))))
241 return qe_port->bd_virt + (addr - qe_port->bd_dma_addr);
259 struct uart_qe_port *qe_port =
261 struct qe_bd *bdp = qe_port->tx_bd_base;
311 struct uart_qe_port *qe_port =
314 qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
331 static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
336 struct uart_port *port = &qe_port->port;
342 bdp = qe_port->tx_cur;
344 p = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
351 bdp = qe_port->tx_bd_base;
354 qe_port->tx_cur = bdp;
367 bdp = qe_port->tx_cur;
372 p = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
373 while (count < qe_port->tx_fifosize) {
387 bdp = qe_port->tx_bd_base;
391 qe_port->tx_cur = bdp;
415 struct uart_qe_port *qe_port =
419 if (qe_ioread16be(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX)
423 if (qe_uart_tx_pump(qe_port))
424 qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
432 struct uart_qe_port *qe_port =
435 qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
446 struct uart_qe_port *qe_port =
450 ucc_slow_stop_tx(qe_port->us_private);
452 ucc_slow_restart_tx(qe_port->us_private);
459 static void qe_uart_int_rx(struct uart_qe_port *qe_port)
463 struct uart_port *port = &qe_port->port;
472 bdp = qe_port->rx_cur;
492 cp = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
516 bdp = qe_port->rx_bd_base;
523 qe_port->rx_cur = bdp;
567 struct uart_qe_port *qe_port = (struct uart_qe_port *) data;
568 struct ucc_slow __iomem *uccp = qe_port->uccp;
576 uart_handle_break(&qe_port->port);
579 qe_uart_int_rx(qe_port);
582 qe_uart_tx_pump(qe_port);
591 static void qe_uart_initbd(struct uart_qe_port *qe_port)
600 bd_virt = qe_port->bd_virt;
601 bdp = qe_port->rx_bd_base;
602 qe_port->rx_cur = qe_port->rx_bd_base;
603 for (i = 0; i < (qe_port->rx_nrfifos - 1); i++) {
605 qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
607 bd_virt += qe_port->rx_fifosize;
613 qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
620 bd_virt = qe_port->bd_virt +
621 L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
622 qe_port->tx_cur = qe_port->tx_bd_base;
623 bdp = qe_port->tx_bd_base;
624 for (i = 0; i < (qe_port->tx_nrfifos - 1); i++) {
626 qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
628 bd_virt += qe_port->tx_fifosize;
634 qe_setbits_be16(&qe_port->tx_cur->status, BD_SC_P);
638 qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
649 static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
652 struct ucc_slow __iomem *uccp = qe_port->uccp;
653 struct ucc_uart_pram *uccup = qe_port->uccup;
658 ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
663 qe_iowrite16be(qe_port->rx_fifosize, &uccup->common.mrblr);
757 cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
761 cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
772 struct uart_qe_port *qe_port =
785 qe_uart_initbd(qe_port);
786 qe_uart_init_ucc(qe_port);
790 qe_port);
797 qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
798 ucc_slow_enable(qe_port->us_private, COMM_DIR_RX_AND_TX);
808 struct uart_qe_port *qe_port =
810 struct ucc_slow __iomem *uccp = qe_port->uccp;
825 if (qe_port->wait_closing) {
828 schedule_timeout(qe_port->wait_closing);
832 ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
836 ucc_slow_graceful_stop_tx(qe_port->us_private);
837 qe_uart_initbd(qe_port);
839 free_irq(port->irq, qe_port);
848 struct uart_qe_port *qe_port =
850 struct ucc_slow __iomem *uccp = qe_port->uccp;
854 struct ucc_uart_pram __iomem *uccup = qe_port->uccup;
959 qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
960 qe_setbrg(qe_port->us_info.tx_clock, baud, 1);
962 qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
963 qe_setbrg(qe_port->us_info.tx_clock, baud, 16);
983 struct uart_qe_port *qe_port =
985 struct ucc_slow_info *us_info = &qe_port->us_info;
994 qe_port->ucc_num);
998 qe_port->us_private = uccs;
999 qe_port->uccp = uccs->us_regs;
1000 qe_port->uccup = (struct ucc_uart_pram *) uccs->us_pram;
1001 qe_port->rx_bd_base = uccs->rx_bd;
1002 qe_port->tx_bd_base = uccs->tx_bd;
1008 rx_size = L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
1009 tx_size = L1_CACHE_ALIGN(qe_port->tx_nrfifos * qe_port->tx_fifosize);
1018 qe_port->bd_virt = bd_virt;
1019 qe_port->bd_dma_addr = bd_dma_addr;
1020 qe_port->bd_size = rx_size + tx_size;
1022 qe_port->rx_buf = bd_virt;
1023 qe_port->tx_buf = qe_port->rx_buf + rx_size;
1049 struct uart_qe_port *qe_port =
1051 struct ucc_slow_private *uccs = qe_port->us_private;
1053 dma_free_coherent(port->dev, qe_port->bd_size, qe_port->bd_virt,
1054 qe_port->bd_dma_addr);
1258 struct uart_qe_port *qe_port = NULL;
1270 qe_port = kzalloc(sizeof(struct uart_qe_port), GFP_KERNEL);
1271 if (!qe_port) {
1287 qe_port->port.mapbase = res.start;
1304 qe_port->ucc_num = val - 1;
1320 qe_port->us_info.rx_clock = qe_clock_source(sprop);
1321 if ((qe_port->us_info.rx_clock < QE_BRG1) ||
1322 (qe_port->us_info.rx_clock > QE_BRG16)) {
1330 qe_port->us_info.tx_clock = qe_port->us_info.rx_clock;
1338 qe_port->us_info.tx_clock = qe_clock_source(sprop);
1340 if ((qe_port->us_info.tx_clock < QE_BRG1) ||
1341 (qe_port->us_info.tx_clock > QE_BRG16)) {
1353 qe_port->port.line = val;
1354 if (qe_port->port.line >= UCC_MAX_UART) {
1361 qe_port->port.irq = irq_of_parse_and_map(np, 0);
1362 if (qe_port->port.irq == 0) {
1364 qe_port->ucc_num + 1);
1391 qe_port->port.uartclk = val;
1412 qe_port->port.uartclk = val / 2;
1421 spin_lock_init(&qe_port->port.lock);
1422 qe_port->np = np;
1423 qe_port->port.dev = &ofdev->dev;
1424 qe_port->port.ops = &qe_uart_pops;
1425 qe_port->port.iotype = UPIO_MEM;
1427 qe_port->tx_nrfifos = TX_NUM_FIFO;
1428 qe_port->tx_fifosize = TX_BUF_SIZE;
1429 qe_port->rx_nrfifos = RX_NUM_FIFO;
1430 qe_port->rx_fifosize = RX_BUF_SIZE;
1432 qe_port->wait_closing = UCC_WAIT_CLOSING;
1433 qe_port->port.fifosize = 512;
1434 qe_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
1436 qe_port->us_info.ucc_num = qe_port->ucc_num;
1437 qe_port->us_info.regs = (phys_addr_t) res.start;
1438 qe_port->us_info.irq = qe_port->port.irq;
1440 qe_port->us_info.rx_bd_ring_len = qe_port->rx_nrfifos;
1441 qe_port->us_info.tx_bd_ring_len = qe_port->tx_nrfifos;
1444 qe_port->us_info.init_tx = 1;
1445 qe_port->us_info.init_rx = 1;
1451 ret = uart_add_one_port(&ucc_uart_driver, &qe_port->port);
1454 qe_port->port.line);
1458 platform_set_drvdata(ofdev, qe_port);
1461 qe_port->ucc_num + 1, qe_port->port.line);
1465 qe_port->port.line, SERIAL_QE_MAJOR,
1466 SERIAL_QE_MINOR + qe_port->port.line);
1472 kfree(qe_port);
1478 struct uart_qe_port *qe_port = platform_get_drvdata(ofdev);
1480 dev_info(&ofdev->dev, "removing /dev/ttyQE%u\n", qe_port->port.line);
1482 uart_remove_one_port(&ucc_uart_driver, &qe_port->port);
1484 kfree(qe_port);