Lines Matching refs:up
268 static void sunzilog_maybe_update_regs(struct uart_sunzilog_port *up,
271 if (!ZS_REGS_HELD(up)) {
272 if (ZS_TX_ACTIVE(up)) {
273 up->flags |= SUNZILOG_FLAG_REGS_HELD;
275 __load_zsregs(channel, up->curregs);
280 static void sunzilog_change_mouse_baud(struct uart_sunzilog_port *up)
282 unsigned int cur_cflag = up->cflag;
285 up->cflag &= ~CBAUD;
286 up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
289 up->curregs[R12] = (brg & 0xff);
290 up->curregs[R13] = (brg >> 8) & 0xff;
291 sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(&up->port));
294 static void sunzilog_kbdms_receive_chars(struct uart_sunzilog_port *up,
297 if (ZS_IS_KEYB(up)) {
300 if (up->serio_open)
301 serio_interrupt(&up->serio, ch, 0);
303 } else if (ZS_IS_MOUSE(up)) {
308 sunzilog_change_mouse_baud(up);
315 if (up->serio_open)
316 serio_interrupt(&up->serio, ch, 0);
324 sunzilog_receive_chars(struct uart_sunzilog_port *up,
330 if (up->port.state != NULL) /* Unopened serial console */
331 port = &up->port.state->port;
357 ch &= up->parity_mask;
359 if (unlikely(ZS_IS_KEYB(up)) || unlikely(ZS_IS_MOUSE(up))) {
360 sunzilog_kbdms_receive_chars(up, ch, 0);
366 up->port.icount.rx++;
370 up->port.icount.brk++;
371 if (uart_handle_break(&up->port))
375 up->port.icount.parity++;
377 up->port.icount.frame++;
379 up->port.icount.overrun++;
380 r1 &= up->port.read_status_mask;
388 if (uart_handle_sysrq_char(&up->port, ch) || !port)
391 if (up->port.ignore_status_mask == 0xff ||
392 (r1 & up->port.ignore_status_mask) == 0) {
402 static void sunzilog_status_handle(struct uart_sunzilog_port *up,
415 if (ZS_IS_MOUSE(up))
416 sunzilog_kbdms_receive_chars(up, 0, 1);
417 if (ZS_IS_CONS(up)) {
432 if (ZS_WANTS_MODEM_STATUS(up)) {
434 up->port.icount.dsr++;
440 if ((status ^ up->prev_status) ^ DCD)
441 uart_handle_dcd_change(&up->port,
443 if ((status ^ up->prev_status) ^ CTS)
444 uart_handle_cts_change(&up->port,
447 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
450 up->prev_status = status;
453 static void sunzilog_transmit_chars(struct uart_sunzilog_port *up,
458 if (ZS_IS_CONS(up)) {
474 up->flags &= ~SUNZILOG_FLAG_TX_ACTIVE;
476 if (ZS_REGS_HELD(up)) {
477 __load_zsregs(channel, up->curregs);
478 up->flags &= ~SUNZILOG_FLAG_REGS_HELD;
481 if (ZS_TX_STOPPED(up)) {
482 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
486 if (up->port.x_char) {
487 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
488 writeb(up->port.x_char, &channel->data);
492 up->port.icount.tx++;
493 up->port.x_char = 0;
497 if (up->port.state == NULL)
499 xmit = &up->port.state->xmit;
503 if (uart_tx_stopped(&up->port))
506 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
512 up->port.icount.tx++;
515 uart_write_wakeup(&up->port);
527 struct uart_sunzilog_port *up = dev_id;
529 while (up) {
531 = ZILOG_CHANNEL_FROM_PORT(&up->port);
535 spin_lock(&up->port.lock);
546 port = sunzilog_receive_chars(up, channel);
548 sunzilog_status_handle(up, channel);
550 sunzilog_transmit_chars(up, channel);
552 spin_unlock(&up->port.lock);
558 up = up->next;
559 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
561 spin_lock(&up->port.lock);
569 port = sunzilog_receive_chars(up, channel);
571 sunzilog_status_handle(up, channel);
573 sunzilog_transmit_chars(up, channel);
575 spin_unlock(&up->port.lock);
580 up = up->next;
644 struct uart_sunzilog_port *up =
661 up->curregs[R5] |= set_bits;
662 up->curregs[R5] &= ~clear_bits;
663 write_zsreg(channel, R5, up->curregs[R5]);
669 struct uart_sunzilog_port *up =
672 up->flags |= SUNZILOG_FLAG_TX_STOPPED;
678 struct uart_sunzilog_port *up =
683 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
684 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
716 uart_write_wakeup(&up->port);
723 struct uart_sunzilog_port *up = UART_ZILOG(port);
726 if (ZS_IS_CONS(up))
732 up->curregs[R1] &= ~RxINT_MASK;
733 sunzilog_maybe_update_regs(up, channel);
739 struct uart_sunzilog_port *up =
744 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
745 if (new_reg != up->curregs[R15]) {
746 up->curregs[R15] = new_reg;
749 write_zsreg(channel, R15, up->curregs[R15] & ~WR7pEN);
756 struct uart_sunzilog_port *up =
771 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
772 if (new_reg != up->curregs[R5]) {
773 up->curregs[R5] = new_reg;
776 write_zsreg(channel, R5, up->curregs[R5]);
782 static void __sunzilog_startup(struct uart_sunzilog_port *up)
786 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
787 up->prev_status = readb(&channel->control);
790 up->curregs[R3] |= RxENAB;
791 up->curregs[R5] |= TxENAB;
793 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
794 sunzilog_maybe_update_regs(up, channel);
799 struct uart_sunzilog_port *up = UART_ZILOG(port);
802 if (ZS_IS_CONS(up))
806 __sunzilog_startup(up);
838 struct uart_sunzilog_port *up = UART_ZILOG(port);
842 if (ZS_IS_CONS(up))
850 up->curregs[R3] &= ~RxENAB;
851 up->curregs[R5] &= ~TxENAB;
854 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
855 up->curregs[R5] &= ~SND_BRK;
856 sunzilog_maybe_update_regs(up, channel);
865 sunzilog_convert_to_zs(struct uart_sunzilog_port *up, unsigned int cflag,
869 up->curregs[R10] = NRZ;
870 up->curregs[R11] = TCBR | RCBR;
873 up->curregs[R4] &= ~XCLK_MASK;
874 up->curregs[R4] |= X16CLK;
875 up->curregs[R12] = brg & 0xff;
876 up->curregs[R13] = (brg >> 8) & 0xff;
877 up->curregs[R14] = BRSRC | BRENAB;
880 up->curregs[R3] &= ~RxN_MASK;
881 up->curregs[R5] &= ~TxN_MASK;
884 up->curregs[R3] |= Rx5;
885 up->curregs[R5] |= Tx5;
886 up->parity_mask = 0x1f;
889 up->curregs[R3] |= Rx6;
890 up->curregs[R5] |= Tx6;
891 up->parity_mask = 0x3f;
894 up->curregs[R3] |= Rx7;
895 up->curregs[R5] |= Tx7;
896 up->parity_mask = 0x7f;
900 up->curregs[R3] |= Rx8;
901 up->curregs[R5] |= Tx8;
902 up->parity_mask = 0xff;
905 up->curregs[R4] &= ~0x0c;
907 up->curregs[R4] |= SB2;
909 up->curregs[R4] |= SB1;
911 up->curregs[R4] |= PAR_ENAB;
913 up->curregs[R4] &= ~PAR_ENAB;
915 up->curregs[R4] |= PAR_EVEN;
917 up->curregs[R4] &= ~PAR_EVEN;
919 up->port.read_status_mask = Rx_OVR;
921 up->port.read_status_mask |= CRC_ERR | PAR_ERR;
923 up->port.read_status_mask |= BRK_ABRT;
925 up->port.ignore_status_mask = 0;
927 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
929 up->port.ignore_status_mask |= BRK_ABRT;
931 up->port.ignore_status_mask |= Rx_OVR;
935 up->port.ignore_status_mask = 0xff;
943 struct uart_sunzilog_port *up =
950 spin_lock_irqsave(&up->port.lock, flags);
954 sunzilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
956 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
957 up->flags |= SUNZILOG_FLAG_MODEM_STATUS;
959 up->flags &= ~SUNZILOG_FLAG_MODEM_STATUS;
961 up->cflag = termios->c_cflag;
963 sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
967 spin_unlock_irqrestore(&up->port.lock, flags);
972 struct uart_sunzilog_port *up = UART_ZILOG(port);
974 return (up->flags & SUNZILOG_FLAG_ESCC) ? "zs (ESCC)" : "zs";
1004 struct uart_sunzilog_port *up =
1007 = ZILOG_CHANNEL_FROM_PORT(&up->port);
1032 ch &= up->parity_mask;
1039 struct uart_sunzilog_port *up =
1042 sunzilog_putchar(&up->port, ch);
1084 struct uart_sunzilog_port *up;
1095 up = &sunzilog_port_table[i];
1097 spin_lock_init(&up->port.lock);
1100 sunzilog_irq_chain = up;
1103 up->next = up + 1;
1105 up->next = NULL;
1156 struct uart_sunzilog_port *up = serio->port_data;
1161 sunzilog_putchar(&up->port, ch);
1170 struct uart_sunzilog_port *up = serio->port_data;
1175 if (!up->serio_open) {
1176 up->serio_open = 1;
1187 struct uart_sunzilog_port *up = serio->port_data;
1191 up->serio_open = 0;
1201 struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1205 if (up->port.sysrq || oops_in_progress)
1206 locked = spin_trylock_irqsave(&up->port.lock, flags);
1208 spin_lock_irqsave(&up->port.lock, flags);
1210 uart_console_write(&up->port, s, count, sunzilog_putchar);
1214 spin_unlock_irqrestore(&up->port.lock, flags);
1219 struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1223 if (up->port.type != PORT_SUNZILOG)
1230 sunserial_console_termios(con, up->port.dev->of_node);
1249 spin_lock_irqsave(&up->port.lock, flags);
1251 up->curregs[R15] |= BRKIE;
1252 sunzilog_convert_to_zs(up, con->cflag, 0, brg);
1254 sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1255 __sunzilog_startup(up);
1257 spin_unlock_irqrestore(&up->port.lock, flags);
1281 static void sunzilog_init_kbdms(struct uart_sunzilog_port *up)
1285 if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1286 up->cflag = B1200 | CS8 | CLOCAL | CREAD;
1289 up->cflag = B4800 | CS8 | CLOCAL | CREAD;
1293 up->curregs[R15] |= BRKIE;
1295 sunzilog_convert_to_zs(up, up->cflag, 0, brg);
1296 sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1297 __sunzilog_startup(up);
1301 static void sunzilog_register_serio(struct uart_sunzilog_port *up)
1303 struct serio *serio = &up->serio;
1305 serio->port_data = up;
1308 if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1317 ((up->flags & SUNZILOG_FLAG_CONS_KEYB) ?
1324 serio->dev.parent = up->port.dev;
1330 static void sunzilog_init_hw(struct uart_sunzilog_port *up)
1336 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1338 spin_lock_irqsave(&up->port.lock, flags);
1339 if (ZS_IS_CHANNEL_A(up)) {
1345 if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1347 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1348 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1349 up->curregs[R3] = RxENAB | Rx8;
1350 up->curregs[R5] = TxENAB | Tx8;
1351 up->curregs[R6] = 0x00; /* SDLC Address */
1352 up->curregs[R7] = 0x7E; /* SDLC Flag */
1353 up->curregs[R9] = NV;
1354 up->curregs[R7p] = 0x00;
1355 sunzilog_init_kbdms(up);
1357 if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
1358 up->curregs[R9] |= MIE;
1359 write_zsreg(channel, R9, up->curregs[R9]);
1362 up->parity_mask = 0xff;
1363 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1364 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1365 up->curregs[R3] = RxENAB | Rx8;
1366 up->curregs[R5] = TxENAB | Tx8;
1367 up->curregs[R6] = 0x00; /* SDLC Address */
1368 up->curregs[R7] = 0x7E; /* SDLC Flag */
1369 up->curregs[R9] = NV;
1370 up->curregs[R10] = NRZ;
1371 up->curregs[R11] = TCBR | RCBR;
1374 up->curregs[R12] = (brg & 0xff);
1375 up->curregs[R13] = (brg >> 8) & 0xff;
1376 up->curregs[R14] = BRSRC | BRENAB;
1377 up->curregs[R15] = FIFOEN; /* Use FIFO if on ESCC */
1378 up->curregs[R7p] = TxFIFO_LVL | RxFIFO_LVL;
1379 if (__load_zsregs(channel, up->curregs)) {
1380 up->flags |= SUNZILOG_FLAG_ESCC;
1383 if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
1384 up->curregs[R9] |= MIE;
1385 write_zsreg(channel, R9, up->curregs[R9]);
1388 spin_unlock_irqrestore(&up->port.lock, flags);
1391 if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1393 sunzilog_register_serio(up);
1403 struct uart_sunzilog_port *up;
1428 up = &sunzilog_port_table[inst * 2];
1431 up[0].port.mapbase = op->resource[0].start + 0x00;
1432 up[0].port.membase = (void __iomem *) &rp->channelA;
1433 up[0].port.iotype = UPIO_MEM;
1434 up[0].port.irq = op->archdata.irqs[0];
1435 up[0].port.uartclk = ZS_CLOCK;
1436 up[0].port.fifosize = 1;
1437 up[0].port.ops = &sunzilog_pops;
1438 up[0].port.type = PORT_SUNZILOG;
1439 up[0].port.flags = 0;
1440 up[0].port.line = (inst * 2) + 0;
1441 up[0].port.dev = &op->dev;
1442 up[0].flags |= SUNZILOG_FLAG_IS_CHANNEL_A;
1443 up[0].port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SUNZILOG_CONSOLE);
1445 up[0].flags |= SUNZILOG_FLAG_CONS_KEYB;
1446 sunzilog_init_hw(&up[0]);
1449 up[1].port.mapbase = op->resource[0].start + 0x04;
1450 up[1].port.membase = (void __iomem *) &rp->channelB;
1451 up[1].port.iotype = UPIO_MEM;
1452 up[1].port.irq = op->archdata.irqs[0];
1453 up[1].port.uartclk = ZS_CLOCK;
1454 up[1].port.fifosize = 1;
1455 up[1].port.ops = &sunzilog_pops;
1456 up[1].port.type = PORT_SUNZILOG;
1457 up[1].port.flags = 0;
1458 up[1].port.line = (inst * 2) + 1;
1459 up[1].port.dev = &op->dev;
1460 up[1].flags |= 0;
1461 up[1].port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SUNZILOG_CONSOLE);
1463 up[1].flags |= SUNZILOG_FLAG_CONS_MOUSE;
1464 sunzilog_init_hw(&up[1]);
1468 &sunzilog_reg, up[0].port.line,
1470 up->flags |= SUNZILOG_FLAG_IS_CONS;
1471 err = uart_add_one_port(&sunzilog_reg, &up[0].port);
1478 &sunzilog_reg, up[1].port.line,
1480 up->flags |= SUNZILOG_FLAG_IS_CONS;
1481 err = uart_add_one_port(&sunzilog_reg, &up[1].port);
1483 uart_remove_one_port(&sunzilog_reg, &up[0].port);
1493 (unsigned long long) up[0].port.mapbase,
1494 op->archdata.irqs[0], sunzilog_type(&up[0].port));
1498 (unsigned long long) up[1].port.mapbase,
1499 op->archdata.irqs[0], sunzilog_type(&up[1].port));
1503 platform_set_drvdata(op, &up[0]);
1508 static void zs_remove_one(struct uart_sunzilog_port *up)
1510 if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up)) {
1512 serio_unregister_port(&up->serio);
1515 uart_remove_one_port(&sunzilog_reg, &up->port);
1520 struct uart_sunzilog_port *up = platform_get_drvdata(op);
1523 zs_remove_one(&up[0]);
1524 zs_remove_one(&up[1]);
1526 regs = sunzilog_chip_regs[up[0].port.line / 2];
1580 struct uart_sunzilog_port *up = sunzilog_irq_chain;
1587 while (up) {
1590 /* printk (KERN_INFO "Enable IRQ for ZILOG Hardware %p\n", up); */
1591 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1592 up->flags |= SUNZILOG_FLAG_ISR_HANDLER;
1593 up->curregs[R9] |= MIE;
1594 write_zsreg(channel, R9, up->curregs[R9]);
1595 up = up->next;
1621 struct uart_sunzilog_port *up = sunzilog_irq_chain;
1624 while (up) {
1627 /* printk (KERN_INFO "Disable IRQ for ZILOG Hardware %p\n", up); */
1628 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1629 up->flags &= ~SUNZILOG_FLAG_ISR_HANDLER;
1630 up->curregs[R9] &= ~MIE;
1631 write_zsreg(channel, R9, up->curregs[R9]);
1632 up = up->next;