Lines Matching refs:curregs
77 unsigned char curregs[NUM_ZSREGS];
275 __load_zsregs(channel, up->curregs);
289 up->curregs[R12] = (brg & 0xff);
290 up->curregs[R13] = (brg >> 8) & 0xff;
477 __load_zsregs(channel, up->curregs);
661 up->curregs[R5] |= set_bits;
662 up->curregs[R5] &= ~clear_bits;
663 write_zsreg(channel, R5, up->curregs[R5]);
732 up->curregs[R1] &= ~RxINT_MASK;
744 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
745 if (new_reg != up->curregs[R15]) {
746 up->curregs[R15] = new_reg;
749 write_zsreg(channel, R15, up->curregs[R15] & ~WR7pEN);
771 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
772 if (new_reg != up->curregs[R5]) {
773 up->curregs[R5] = new_reg;
776 write_zsreg(channel, R5, up->curregs[R5]);
790 up->curregs[R3] |= RxENAB;
791 up->curregs[R5] |= TxENAB;
793 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
850 up->curregs[R3] &= ~RxENAB;
851 up->curregs[R5] &= ~TxENAB;
854 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
855 up->curregs[R5] &= ~SND_BRK;
869 up->curregs[R10] = NRZ;
870 up->curregs[R11] = TCBR | RCBR;
873 up->curregs[R4] &= ~XCLK_MASK;
874 up->curregs[R4] |= X16CLK;
875 up->curregs[R12] = brg & 0xff;
876 up->curregs[R13] = (brg >> 8) & 0xff;
877 up->curregs[R14] = BRSRC | BRENAB;
880 up->curregs[R3] &= ~RxN_MASK;
881 up->curregs[R5] &= ~TxN_MASK;
884 up->curregs[R3] |= Rx5;
885 up->curregs[R5] |= Tx5;
889 up->curregs[R3] |= Rx6;
890 up->curregs[R5] |= Tx6;
894 up->curregs[R3] |= Rx7;
895 up->curregs[R5] |= Tx7;
900 up->curregs[R3] |= Rx8;
901 up->curregs[R5] |= Tx8;
905 up->curregs[R4] &= ~0x0c;
907 up->curregs[R4] |= SB2;
909 up->curregs[R4] |= SB1;
911 up->curregs[R4] |= PAR_ENAB;
913 up->curregs[R4] &= ~PAR_ENAB;
915 up->curregs[R4] |= PAR_EVEN;
917 up->curregs[R4] &= ~PAR_EVEN;
1251 up->curregs[R15] |= BRKIE;
1293 up->curregs[R15] |= BRKIE;
1347 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1348 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1349 up->curregs[R3] = RxENAB | Rx8;
1350 up->curregs[R5] = TxENAB | Tx8;
1351 up->curregs[R6] = 0x00; /* SDLC Address */
1352 up->curregs[R7] = 0x7E; /* SDLC Flag */
1353 up->curregs[R9] = NV;
1354 up->curregs[R7p] = 0x00;
1358 up->curregs[R9] |= MIE;
1359 write_zsreg(channel, R9, up->curregs[R9]);
1363 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1364 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1365 up->curregs[R3] = RxENAB | Rx8;
1366 up->curregs[R5] = TxENAB | Tx8;
1367 up->curregs[R6] = 0x00; /* SDLC Address */
1368 up->curregs[R7] = 0x7E; /* SDLC Flag */
1369 up->curregs[R9] = NV;
1370 up->curregs[R10] = NRZ;
1371 up->curregs[R11] = TCBR | RCBR;
1374 up->curregs[R12] = (brg & 0xff);
1375 up->curregs[R13] = (brg >> 8) & 0xff;
1376 up->curregs[R14] = BRSRC | BRENAB;
1377 up->curregs[R15] = FIFOEN; /* Use FIFO if on ESCC */
1378 up->curregs[R7p] = TxFIFO_LVL | RxFIFO_LVL;
1379 if (__load_zsregs(channel, up->curregs)) {
1384 up->curregs[R9] |= MIE;
1385 write_zsreg(channel, R9, up->curregs[R9]);
1593 up->curregs[R9] |= MIE;
1594 write_zsreg(channel, R9, up->curregs[R9]);
1630 up->curregs[R9] &= ~MIE;
1631 write_zsreg(channel, R9, up->curregs[R9]);