Lines Matching refs:up
91 static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
93 int timeout = up->tec_timeout;
95 while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
99 static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
101 int timeout = up->cec_timeout;
103 while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
108 receive_chars(struct uart_sunsab_port *up,
118 if (up->port.state != NULL) /* Unopened serial console */
119 port = &up->port.state->port;
128 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
134 sunsab_cec_wait(up);
135 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
144 buf[i] = readb(&up->regs->r.rfifo[i]);
148 sunsab_cec_wait(up);
149 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
154 (up->port.line == up->port.cons->index))
161 up->port.icount.brk++;
162 uart_handle_break(&up->port);
170 up->port.icount.rx++;
182 up->port.icount.brk++;
189 if (uart_handle_break(&up->port))
192 up->port.icount.parity++;
194 up->port.icount.frame++;
196 up->port.icount.overrun++;
201 stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
202 stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
212 if (uart_handle_sysrq_char(&up->port, ch) || !port)
215 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
216 (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0)
231 static void transmit_chars(struct uart_sunsab_port *up,
234 struct circ_buf *xmit = &up->port.state->xmit;
238 up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
239 writeb(up->interrupt_mask1, &up->regs->w.imr1);
240 set_bit(SAB82532_ALLS, &up->irqflags);
248 if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
251 set_bit(SAB82532_XPR, &up->irqflags);
252 sunsab_tx_idle(up);
254 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
255 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
256 writeb(up->interrupt_mask1, &up->regs->w.imr1);
260 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
261 writeb(up->interrupt_mask1, &up->regs->w.imr1);
262 clear_bit(SAB82532_ALLS, &up->irqflags);
265 clear_bit(SAB82532_XPR, &up->irqflags);
266 for (i = 0; i < up->port.fifosize; i++) {
268 &up->regs->w.xfifo[i]);
270 up->port.icount.tx++;
276 sunsab_cec_wait(up);
277 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
280 uart_write_wakeup(&up->port);
283 sunsab_stop_tx(&up->port);
286 static void check_status(struct uart_sunsab_port *up,
290 uart_handle_dcd_change(&up->port,
291 !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
294 uart_handle_cts_change(&up->port,
295 (readb(&up->regs->r.star) & SAB82532_STAR_CTS));
297 if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
298 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
299 up->port.icount.dsr++;
302 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
307 struct uart_sunsab_port *up = dev_id;
313 spin_lock_irqsave(&up->port.lock, flags);
316 gis = readb(&up->regs->r.gis) >> up->gis_shift;
318 status.sreg.isr0 = readb(&up->regs->r.isr0);
320 status.sreg.isr1 = readb(&up->regs->r.isr1);
326 port = receive_chars(up, &status);
329 check_status(up, &status);
331 transmit_chars(up, &status);
334 spin_unlock_irqrestore(&up->port.lock, flags);
345 struct uart_sunsab_port *up =
350 if (test_bit(SAB82532_ALLS, &up->irqflags))
361 struct uart_sunsab_port *up =
365 up->cached_mode &= ~SAB82532_MODE_FRTS;
366 up->cached_mode |= SAB82532_MODE_RTS;
368 up->cached_mode |= (SAB82532_MODE_FRTS |
372 up->cached_pvr &= ~(up->pvr_dtr_bit);
374 up->cached_pvr |= up->pvr_dtr_bit;
377 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
378 if (test_bit(SAB82532_XPR, &up->irqflags))
379 sunsab_tx_idle(up);
385 struct uart_sunsab_port *up =
392 val = readb(&up->regs->r.pvr);
393 result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
395 val = readb(&up->regs->r.vstr);
398 val = readb(&up->regs->r.star);
407 struct uart_sunsab_port *up =
410 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
411 writeb(up->interrupt_mask1, &up->regs->w.imr1);
415 static void sunsab_tx_idle(struct uart_sunsab_port *up)
417 if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) {
420 clear_bit(SAB82532_REGS_PENDING, &up->irqflags);
421 writeb(up->cached_mode, &up->regs->rw.mode);
422 writeb(up->cached_pvr, &up->regs->rw.pvr);
423 writeb(up->cached_dafo, &up->regs->w.dafo);
425 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr);
426 tmp = readb(&up->regs->rw.ccr2);
428 tmp |= (up->cached_ebrg >> 2) & 0xc0;
429 writeb(tmp, &up->regs->rw.ccr2);
436 struct uart_sunsab_port *up =
438 struct circ_buf *xmit = &up->port.state->xmit;
444 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
445 writeb(up->interrupt_mask1, &up->regs->w.imr1);
447 if (!test_bit(SAB82532_XPR, &up->irqflags))
450 clear_bit(SAB82532_ALLS, &up->irqflags);
451 clear_bit(SAB82532_XPR, &up->irqflags);
453 for (i = 0; i < up->port.fifosize; i++) {
455 &up->regs->w.xfifo[i]);
457 up->port.icount.tx++;
463 sunsab_cec_wait(up);
464 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
470 struct uart_sunsab_port *up =
477 spin_lock_irqsave(&up->port.lock, flags);
479 sunsab_tec_wait(up);
480 writeb(ch, &up->regs->w.tic);
482 spin_unlock_irqrestore(&up->port.lock, flags);
488 struct uart_sunsab_port *up =
491 up->interrupt_mask0 |= SAB82532_IMR0_TCD;
492 writeb(up->interrupt_mask1, &up->regs->w.imr0);
498 struct uart_sunsab_port *up =
503 spin_lock_irqsave(&up->port.lock, flags);
505 val = up->cached_dafo;
510 up->cached_dafo = val;
512 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
513 if (test_bit(SAB82532_XPR, &up->irqflags))
514 sunsab_tx_idle(up);
516 spin_unlock_irqrestore(&up->port.lock, flags);
522 struct uart_sunsab_port *up =
526 int err = request_irq(up->port.irq, sunsab_interrupt,
527 IRQF_SHARED, "sab", up);
531 spin_lock_irqsave(&up->port.lock, flags);
536 sunsab_cec_wait(up);
537 sunsab_tec_wait(up);
542 writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
543 sunsab_cec_wait(up);
544 writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
549 (void) readb(&up->regs->r.isr0);
550 (void) readb(&up->regs->r.isr1);
555 writeb(0, &up->regs->w.ccr0); /* power-down */
557 SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
558 writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
560 SAB82532_CCR2_TOE, &up->regs->w.ccr2);
561 writeb(0, &up->regs->w.ccr3);
562 writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
563 up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
565 writeb(up->cached_mode, &up->regs->w.mode);
566 writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
568 tmp = readb(&up->regs->rw.ccr0);
569 tmp |= SAB82532_CCR0_PU; /* power-up */
570 writeb(tmp, &up->regs->rw.ccr0);
575 up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
577 writeb(up->interrupt_mask0, &up->regs->w.imr0);
578 up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
582 writeb(up->interrupt_mask1, &up->regs->w.imr1);
583 set_bit(SAB82532_ALLS, &up->irqflags);
584 set_bit(SAB82532_XPR, &up->irqflags);
586 spin_unlock_irqrestore(&up->port.lock, flags);
594 struct uart_sunsab_port *up =
598 spin_lock_irqsave(&up->port.lock, flags);
601 up->interrupt_mask0 = 0xff;
602 writeb(up->interrupt_mask0, &up->regs->w.imr0);
603 up->interrupt_mask1 = 0xff;
604 writeb(up->interrupt_mask1, &up->regs->w.imr1);
607 up->cached_dafo = readb(&up->regs->rw.dafo);
608 up->cached_dafo &= ~SAB82532_DAFO_XBRK;
609 writeb(up->cached_dafo, &up->regs->rw.dafo);
612 up->cached_mode &= ~SAB82532_MODE_RAC;
613 writeb(up->cached_mode, &up->regs->rw.mode);
627 tmp = readb(&up->regs->rw.ccr0);
629 writeb(tmp, &up->regs->rw.ccr0);
632 spin_unlock_irqrestore(&up->port.lock, flags);
633 free_irq(up->port.irq, up);
679 static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
711 up->cached_dafo = dafo;
715 up->cached_ebrg = n | (m << 6);
717 up->tec_timeout = (10 * 1000000) / baud;
718 up->cec_timeout = up->tec_timeout >> 2;
729 up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
732 up->port.read_status_mask |= (SAB82532_ISR1_CSC |
736 up->port.read_status_mask |= (SAB82532_ISR0_PERR |
739 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
744 up->port.ignore_status_mask = 0;
746 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
749 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
755 up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
762 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
765 uart_update_timeout(&up->port, cflag,
766 (up->port.uartclk / (16 * quot)));
771 up->cached_mode |= SAB82532_MODE_RAC;
772 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
773 if (test_bit(SAB82532_XPR, &up->irqflags))
774 sunsab_tx_idle(up);
781 struct uart_sunsab_port *up =
787 spin_lock_irqsave(&up->port.lock, flags);
788 sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);
789 spin_unlock_irqrestore(&up->port.lock, flags);
794 struct uart_sunsab_port *up = (void *)port;
797 sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
851 struct uart_sunsab_port *up =
854 sunsab_tec_wait(up);
855 writeb(c, &up->regs->w.tic);
860 struct uart_sunsab_port *up = &sunsab_ports[con->index];
864 if (up->port.sysrq || oops_in_progress)
865 locked = spin_trylock_irqsave(&up->port.lock, flags);
867 spin_lock_irqsave(&up->port.lock, flags);
869 uart_console_write(&up->port, s, n, sunsab_console_putchar);
870 sunsab_tec_wait(up);
873 spin_unlock_irqrestore(&up->port.lock, flags);
878 struct uart_sunsab_port *up = &sunsab_ports[con->index];
888 if (up->port.type != PORT_SUNSAB)
894 sunserial_console_termios(con, up->port.dev->of_node);
915 spin_lock_init(&up->port.lock);
920 sunsab_startup(&up->port);
922 spin_lock_irqsave(&up->port.lock, flags);
927 up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
929 writeb(up->interrupt_mask0, &up->regs->w.imr0);
930 up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
934 writeb(up->interrupt_mask1, &up->regs->w.imr1);
936 quot = uart_get_divisor(&up->port, baud);
937 sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);
938 sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
940 spin_unlock_irqrestore(&up->port.lock, flags);
964 static int sunsab_init_one(struct uart_sunsab_port *up,
969 up->port.line = line;
970 up->port.dev = &op->dev;
972 up->port.mapbase = op->resource[0].start + offset;
973 up->port.membase = of_ioremap(&op->resource[0], offset,
976 if (!up->port.membase)
978 up->regs = (union sab82532_async_regs __iomem *) up->port.membase;
980 up->port.irq = op->archdata.irqs[0];
982 up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
983 up->port.iotype = UPIO_MEM;
984 up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SUNSAB_CONSOLE);
986 writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
988 up->port.ops = &sunsab_pops;
989 up->port.type = PORT_SUNSAB;
990 up->port.uartclk = SAB_BASE_BAUD;
992 up->type = readb(&up->regs->r.vstr) & 0x0f;
993 writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
994 writeb(0xff, &up->regs->w.pim);
995 if ((up->port.line & 0x1) == 0) {
996 up->pvr_dsr_bit = (1 << 0);
997 up->pvr_dtr_bit = (1 << 1);
998 up->gis_shift = 2;
1000 up->pvr_dsr_bit = (1 << 3);
1001 up->pvr_dtr_bit = (1 << 2);
1002 up->gis_shift = 0;
1004 up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4);
1005 writeb(up->cached_pvr, &up->regs->w.pvr);
1006 up->cached_mode = readb(&up->regs->rw.mode);
1007 up->cached_mode |= SAB82532_MODE_FRTS;
1008 writeb(up->cached_mode, &up->regs->rw.mode);
1009 up->cached_mode |= SAB82532_MODE_RTS;
1010 writeb(up->cached_mode, &up->regs->rw.mode);
1012 up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
1013 up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
1021 struct uart_sunsab_port *up;
1024 up = &sunsab_ports[inst * 2];
1026 err = sunsab_init_one(&up[0], op,
1032 err = sunsab_init_one(&up[1], op,
1039 &sunsab_reg, up[0].port.line,
1043 &sunsab_reg, up[1].port.line,
1046 err = uart_add_one_port(&sunsab_reg, &up[0].port);
1050 err = uart_add_one_port(&sunsab_reg, &up[1].port);
1054 platform_set_drvdata(op, &up[0]);
1061 uart_remove_one_port(&sunsab_reg, &up[0].port);
1064 up[1].port.membase,
1068 up[0].port.membase,
1076 struct uart_sunsab_port *up = platform_get_drvdata(op);
1078 uart_remove_one_port(&sunsab_reg, &up[1].port);
1079 uart_remove_one_port(&sunsab_reg, &up[0].port);
1081 up[1].port.membase,
1084 up[0].port.membase,