Lines Matching refs:port
37 static void stm32_usart_stop_tx(struct uart_port *port);
38 static void stm32_usart_transmit_chars(struct uart_port *port);
40 static inline struct stm32_port *to_stm32_port(struct uart_port *port)
42 return container_of(port, struct stm32_port, port);
45 static void stm32_usart_set_bits(struct uart_port *port, u32 reg, u32 bits)
49 val = readl_relaxed(port->membase + reg);
51 writel_relaxed(val, port->membase + reg);
54 static void stm32_usart_clr_bits(struct uart_port *port, u32 reg, u32 bits)
58 val = readl_relaxed(port->membase + reg);
60 writel_relaxed(val, port->membase + reg);
100 static int stm32_usart_config_rs485(struct uart_port *port,
103 struct stm32_port *stm32_port = to_stm32_port(port);
109 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
111 port->rs485 = *rs485conf;
116 cr1 = readl_relaxed(port->membase + ofs->cr1);
117 cr3 = readl_relaxed(port->membase + ofs->cr3);
118 usartdiv = readl_relaxed(port->membase + ofs->brr);
126 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv);
140 writel_relaxed(cr3, port->membase + ofs->cr3);
141 writel_relaxed(cr1, port->membase + ofs->cr1);
143 stm32_usart_clr_bits(port, ofs->cr3,
145 stm32_usart_clr_bits(port, ofs->cr1,
149 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
154 static int stm32_usart_init_rs485(struct uart_port *port,
157 struct serial_rs485 *rs485conf = &port->rs485;
166 return uart_get_rs485_mode(port);
169 static int stm32_usart_pending_rx(struct uart_port *port, u32 *sr,
172 struct stm32_port *stm32_port = to_stm32_port(port);
177 *sr = readl_relaxed(port->membase + ofs->isr);
193 static unsigned long stm32_usart_get_char(struct uart_port *port, u32 *sr,
196 struct stm32_port *stm32_port = to_stm32_port(port);
205 c = readl_relaxed(port->membase + ofs->rdr);
213 static void stm32_usart_receive_chars(struct uart_port *port, bool threaded)
215 struct tty_port *tport = &port->state->port;
216 struct stm32_port *stm32_port = to_stm32_port(port);
222 spin_lock(&port->lock);
224 while (stm32_usart_pending_rx(port, &sr, &stm32_port->last_res,
242 port->membase + ofs->icr);
244 c = stm32_usart_get_char(port, &sr, &stm32_port->last_res);
245 port->icount.rx++;
248 port->icount.overrun++;
250 port->icount.parity++;
254 port->icount.brk++;
255 if (uart_handle_break(port))
258 port->icount.frame++;
262 sr &= port->read_status_mask;
274 if (uart_handle_sysrq_char(port, c))
276 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
279 spin_unlock(&port->lock);
286 struct uart_port *port = arg;
287 struct stm32_port *stm32port = to_stm32_port(port);
292 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
296 spin_lock_irqsave(&port->lock, flags);
297 stm32_usart_transmit_chars(port);
298 spin_unlock_irqrestore(&port->lock, flags);
301 static void stm32_usart_tx_interrupt_enable(struct uart_port *port)
303 struct stm32_port *stm32_port = to_stm32_port(port);
311 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE);
313 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
316 static void stm32_usart_tx_interrupt_disable(struct uart_port *port)
318 struct stm32_port *stm32_port = to_stm32_port(port);
322 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE);
324 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
327 static void stm32_usart_transmit_chars_pio(struct uart_port *port)
329 struct stm32_port *stm32_port = to_stm32_port(port);
331 struct circ_buf *xmit = &port->state->xmit;
334 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
340 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
342 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
344 port->icount.tx++;
349 stm32_usart_tx_interrupt_disable(port);
351 stm32_usart_tx_interrupt_enable(port);
354 static void stm32_usart_transmit_chars_dma(struct uart_port *port)
356 struct stm32_port *stm32port = to_stm32_port(port);
358 struct circ_buf *xmit = &port->state->xmit;
397 desc->callback_param = port;
409 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
412 port->icount.tx += count;
417 stm32_usart_transmit_chars_pio(port);
420 static void stm32_usart_transmit_chars(struct uart_port *port)
422 struct stm32_port *stm32_port = to_stm32_port(port);
424 struct circ_buf *xmit = &port->state->xmit;
428 if (port->x_char) {
430 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
434 readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
439 dev_warn(port->dev, "1 character may be erased\n");
441 writel_relaxed(port->x_char, port->membase + ofs->tdr);
442 port->x_char = 0;
443 port->icount.tx++;
445 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
449 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
450 stm32_usart_tx_interrupt_disable(port);
455 stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC);
457 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr);
460 stm32_usart_transmit_chars_dma(port);
462 stm32_usart_transmit_chars_pio(port);
465 uart_write_wakeup(port);
468 stm32_usart_tx_interrupt_disable(port);
473 struct uart_port *port = ptr;
474 struct tty_port *tport = &port->state->port;
475 struct stm32_port *stm32_port = to_stm32_port(port);
479 sr = readl_relaxed(port->membase + ofs->isr);
483 port->membase + ofs->icr);
488 port->membase + ofs->icr);
489 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE);
490 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
495 stm32_usart_receive_chars(port, false);
498 spin_lock(&port->lock);
499 stm32_usart_transmit_chars(port);
500 spin_unlock(&port->lock);
511 struct uart_port *port = ptr;
512 struct stm32_port *stm32_port = to_stm32_port(port);
515 stm32_usart_receive_chars(port, true);
520 static unsigned int stm32_usart_tx_empty(struct uart_port *port)
522 struct stm32_port *stm32_port = to_stm32_port(port);
525 if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC)
531 static void stm32_usart_set_mctrl(struct uart_port *port, unsigned int mctrl)
533 struct stm32_port *stm32_port = to_stm32_port(port);
536 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
537 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE);
539 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
544 static unsigned int stm32_usart_get_mctrl(struct uart_port *port)
546 struct stm32_port *stm32_port = to_stm32_port(port);
555 static void stm32_usart_enable_ms(struct uart_port *port)
557 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios);
560 static void stm32_usart_disable_ms(struct uart_port *port)
562 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios);
566 static void stm32_usart_stop_tx(struct uart_port *port)
568 struct stm32_port *stm32_port = to_stm32_port(port);
569 struct serial_rs485 *rs485conf = &port->rs485;
571 stm32_usart_tx_interrupt_disable(port);
576 stm32_port->port.mctrl & ~TIOCM_RTS);
579 stm32_port->port.mctrl | TIOCM_RTS);
585 static void stm32_usart_start_tx(struct uart_port *port)
587 struct stm32_port *stm32_port = to_stm32_port(port);
588 struct serial_rs485 *rs485conf = &port->rs485;
589 struct circ_buf *xmit = &port->state->xmit;
591 if (uart_circ_empty(xmit) && !port->x_char)
597 stm32_port->port.mctrl | TIOCM_RTS);
600 stm32_port->port.mctrl & ~TIOCM_RTS);
604 stm32_usart_transmit_chars(port);
608 static void stm32_usart_throttle(struct uart_port *port)
610 struct stm32_port *stm32_port = to_stm32_port(port);
614 spin_lock_irqsave(&port->lock, flags);
615 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
617 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
619 spin_unlock_irqrestore(&port->lock, flags);
623 static void stm32_usart_unthrottle(struct uart_port *port)
625 struct stm32_port *stm32_port = to_stm32_port(port);
629 spin_lock_irqsave(&port->lock, flags);
630 stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq);
632 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq);
634 spin_unlock_irqrestore(&port->lock, flags);
638 static void stm32_usart_stop_rx(struct uart_port *port)
640 struct stm32_port *stm32_port = to_stm32_port(port);
643 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
645 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
649 static void stm32_usart_break_ctl(struct uart_port *port, int break_state)
653 static int stm32_usart_startup(struct uart_port *port)
655 struct stm32_port *stm32_port = to_stm32_port(port);
658 const char *name = to_platform_device(port->dev)->name;
662 ret = request_threaded_irq(port->irq, stm32_usart_interrupt,
665 name, port);
671 writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr);
675 stm32_usart_set_bits(port, ofs->cr1, val);
680 static void stm32_usart_shutdown(struct uart_port *port)
682 struct stm32_port *stm32_port = to_stm32_port(port);
689 stm32_usart_disable_ms(port);
697 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr,
702 dev_err(port->dev, "transmission complete not set\n");
707 port->membase + ofs->rqr);
709 stm32_usart_clr_bits(port, ofs->cr1, val);
711 free_irq(port->irq, port);
744 static void stm32_usart_set_termios(struct uart_port *port,
748 struct stm32_port *stm32_port = to_stm32_port(port);
751 struct serial_rs485 *rs485conf = &port->rs485;
762 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
764 spin_lock_irqsave(&port->lock, flags);
766 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
773 dev_err(port->dev, "Transmission is not complete\n");
775 /* Stop serial port and reset value */
776 writel_relaxed(0, port->membase + ofs->cr1);
781 port->membase + ofs->rqr);
789 cr3 = readl_relaxed(port->membase + ofs->cr3);
820 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n"
841 writel_relaxed(bits, port->membase + ofs->rtor);
854 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
856 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
860 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
871 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8);
875 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
880 writel_relaxed(mantissa | fraction, port->membase + ofs->brr);
882 uart_update_timeout(port, cflag, baud);
884 port->read_status_mask = USART_SR_ORE;
886 port->read_status_mask |= USART_SR_PE | USART_SR_FE;
888 port->read_status_mask |= USART_SR_FE;
891 port->ignore_status_mask = 0;
893 port->ignore_status_mask = USART_SR_PE | USART_SR_FE;
895 port->ignore_status_mask |= USART_SR_FE;
901 port->ignore_status_mask |= USART_SR_ORE;
906 port->ignore_status_mask |= USART_SR_DUMMY_RX;
935 writel_relaxed(cr3, port->membase + ofs->cr3);
936 writel_relaxed(cr2, port->membase + ofs->cr2);
937 writel_relaxed(cr1, port->membase + ofs->cr1);
939 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
940 spin_unlock_irqrestore(&port->lock, flags);
943 if (UART_ENABLE_MS(port, termios->c_cflag))
944 stm32_usart_enable_ms(port);
946 stm32_usart_disable_ms(port);
949 static const char *stm32_usart_type(struct uart_port *port)
951 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
954 static void stm32_usart_release_port(struct uart_port *port)
958 static int stm32_usart_request_port(struct uart_port *port)
963 static void stm32_usart_config_port(struct uart_port *port, int flags)
966 port->type = PORT_STM32;
970 stm32_usart_verify_port(struct uart_port *port, struct serial_struct *ser)
976 static void stm32_usart_pm(struct uart_port *port, unsigned int state,
979 struct stm32_port *stm32port = container_of(port,
980 struct stm32_port, port);
987 pm_runtime_get_sync(port->dev);
990 spin_lock_irqsave(&port->lock, flags);
991 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
992 spin_unlock_irqrestore(&port->lock, flags);
993 pm_runtime_put_sync(port->dev);
1023 struct uart_port *port = &stm32port->port;
1031 port->iotype = UPIO_MEM;
1032 port->flags = UPF_BOOT_AUTOCONF;
1033 port->ops = &stm32_uart_ops;
1034 port->dev = &pdev->dev;
1035 port->fifosize = stm32port->info->cfg.fifosize;
1036 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE);
1037 port->irq = ret;
1038 port->rs485_config = stm32_usart_config_rs485;
1040 ret = stm32_usart_init_rs485(port, pdev);
1053 port->membase = devm_ioremap_resource(&pdev->dev, res);
1054 if (IS_ERR(port->membase))
1055 return PTR_ERR(port->membase);
1056 port->mapbase = res->start;
1058 spin_lock_init(&port->lock);
1069 stm32port->port.uartclk = clk_get_rate(stm32port->clk);
1070 if (!stm32port->port.uartclk) {
1075 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0);
1119 stm32_ports[id].port.line = id;
1141 struct uart_port *port = &stm32port->port;
1151 if (uart_console(port))
1170 config.src_addr = port->mapbase + ofs->rdr;
1223 struct uart_port *port = &stm32port->port;
1246 config.dst_addr = port->mapbase + ofs->tdr;
1308 platform_set_drvdata(pdev, &stm32port->port);
1314 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
1362 struct uart_port *port = platform_get_drvdata(pdev);
1363 struct stm32_port *stm32_port = to_stm32_port(port);
1368 err = uart_remove_one_port(&stm32_usart_driver, port);
1376 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
1388 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
1411 static void stm32_usart_console_putchar(struct uart_port *port, int ch)
1413 struct stm32_port *stm32_port = to_stm32_port(port);
1416 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
1419 writel_relaxed(ch, port->membase + ofs->tdr);
1425 struct uart_port *port = &stm32_ports[co->index].port;
1426 struct stm32_port *stm32_port = to_stm32_port(port);
1434 if (port->sysrq)
1437 locked = spin_trylock(&port->lock);
1439 spin_lock(&port->lock);
1442 old_cr1 = readl_relaxed(port->membase + ofs->cr1);
1445 writel_relaxed(new_cr1, port->membase + ofs->cr1);
1447 uart_console_write(port, s, cnt, stm32_usart_console_putchar);
1450 writel_relaxed(old_cr1, port->membase + ofs->cr1);
1453 spin_unlock(&port->lock);
1473 * this to be called during the uart port registration when the
1474 * driver gets probed and the port should be mapped at that point.
1476 if (stm32port->port.mapbase == 0 || !stm32port->port.membase)
1482 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
1510 static void __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port,
1513 struct stm32_port *stm32_port = to_stm32_port(port);
1524 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM);
1525 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_WUFIE);
1527 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM);
1528 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE);
1534 struct uart_port *port = dev_get_drvdata(dev);
1536 uart_suspend_port(&stm32_usart_driver, port);
1539 stm32_usart_serial_en_wakeup(port, true);
1541 stm32_usart_serial_en_wakeup(port, false);
1549 if (console_suspend_enabled || !uart_console(port)) {
1561 struct uart_port *port = dev_get_drvdata(dev);
1566 stm32_usart_serial_en_wakeup(port, false);
1568 return uart_resume_port(&stm32_usart_driver, port);
1573 struct uart_port *port = dev_get_drvdata(dev);
1574 struct stm32_port *stm32port = container_of(port,
1575 struct stm32_port, port);
1584 struct uart_port *port = dev_get_drvdata(dev);
1585 struct stm32_port *stm32port = container_of(port,
1586 struct stm32_port, port);
1636 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");