Lines Matching defs:stm32port
287 struct stm32_port *stm32port = to_stm32_port(port);
288 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
291 dmaengine_terminate_async(stm32port->tx_ch);
293 stm32port->tx_dma_busy = false;
356 struct stm32_port *stm32port = to_stm32_port(port);
357 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
362 if (stm32port->tx_dma_busy)
365 stm32port->tx_dma_busy = true;
373 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count);
382 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one);
384 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two);
387 desc = dmaengine_prep_slave_single(stm32port->tx_ch,
388 stm32port->tx_dma_buf,
402 dmaengine_terminate_async(stm32port->tx_ch);
407 dma_async_issue_pending(stm32port->tx_ch);
979 struct stm32_port *stm32port = container_of(port,
981 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
982 const struct stm32_usart_config *cfg = &stm32port->info->cfg;
1020 static int stm32_usart_init_port(struct stm32_port *stm32port,
1023 struct uart_port *port = &stm32port->port;
1035 port->fifosize = stm32port->info->cfg.fifosize;
1044 if (stm32port->info->cfg.has_wakeup) {
1045 stm32port->wakeirq = platform_get_irq_optional(pdev, 1);
1046 if (stm32port->wakeirq <= 0 && stm32port->wakeirq != -ENXIO)
1047 return stm32port->wakeirq ? : -ENODEV;
1050 stm32port->fifoen = stm32port->info->cfg.has_fifo;
1060 stm32port->clk = devm_clk_get(&pdev->dev, NULL);
1061 if (IS_ERR(stm32port->clk))
1062 return PTR_ERR(stm32port->clk);
1065 ret = clk_prepare_enable(stm32port->clk);
1069 stm32port->port.uartclk = clk_get_rate(stm32port->clk);
1070 if (!stm32port->port.uartclk) {
1075 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0);
1076 if (IS_ERR(stm32port->gpios)) {
1077 ret = PTR_ERR(stm32port->gpios);
1082 if (stm32port->hw_flow_control) {
1083 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) ||
1084 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) {
1094 clk_disable_unprepare(stm32port->clk);
1137 static int stm32_usart_of_dma_rx_probe(struct stm32_port *stm32port,
1140 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1141 struct uart_port *port = &stm32port->port;
1155 stm32port->rx_ch = dma_request_slave_channel(dev, "rx");
1156 if (!stm32port->rx_ch) {
1160 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L,
1161 &stm32port->rx_dma_buf,
1163 if (!stm32port->rx_buf) {
1173 ret = dmaengine_slave_config(stm32port->rx_ch, &config);
1181 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch,
1182 stm32port->rx_dma_buf,
1198 dmaengine_terminate_sync(stm32port->rx_ch);
1203 dma_async_issue_pending(stm32port->rx_ch);
1209 RX_BUF_L, stm32port->rx_buf,
1210 stm32port->rx_dma_buf);
1213 dma_release_channel(stm32port->rx_ch);
1214 stm32port->rx_ch = NULL;
1219 static int stm32_usart_of_dma_tx_probe(struct stm32_port *stm32port,
1222 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1223 struct uart_port *port = &stm32port->port;
1228 stm32port->tx_dma_busy = false;
1231 stm32port->tx_ch = dma_request_slave_channel(dev, "tx");
1232 if (!stm32port->tx_ch) {
1236 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L,
1237 &stm32port->tx_dma_buf,
1239 if (!stm32port->tx_buf) {
1249 ret = dmaengine_slave_config(stm32port->tx_ch, &config);
1260 TX_BUF_L, stm32port->tx_buf,
1261 stm32port->tx_dma_buf);
1264 dma_release_channel(stm32port->tx_ch);
1265 stm32port->tx_ch = NULL;
1272 struct stm32_port *stm32port;
1275 stm32port = stm32_usart_of_get_port(pdev);
1276 if (!stm32port)
1279 stm32port->info = of_device_get_match_data(&pdev->dev);
1280 if (!stm32port->info)
1283 ret = stm32_usart_init_port(stm32port, pdev);
1287 if (stm32port->wakeirq > 0) {
1293 stm32port->wakeirq);
1300 ret = stm32_usart_of_dma_rx_probe(stm32port, pdev);
1304 ret = stm32_usart_of_dma_tx_probe(stm32port, pdev);
1308 platform_set_drvdata(pdev, &stm32port->port);
1314 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
1327 if (stm32port->rx_ch) {
1328 dmaengine_terminate_async(stm32port->rx_ch);
1329 dma_release_channel(stm32port->rx_ch);
1332 if (stm32port->rx_dma_buf)
1334 RX_BUF_L, stm32port->rx_buf,
1335 stm32port->rx_dma_buf);
1337 if (stm32port->tx_ch) {
1338 dmaengine_terminate_async(stm32port->tx_ch);
1339 dma_release_channel(stm32port->tx_ch);
1342 if (stm32port->tx_dma_buf)
1344 TX_BUF_L, stm32port->tx_buf,
1345 stm32port->tx_dma_buf);
1347 if (stm32port->wakeirq > 0)
1351 if (stm32port->wakeirq > 0)
1355 clk_disable_unprepare(stm32port->clk);
1459 struct stm32_port *stm32port;
1468 stm32port = &stm32_ports[co->index];
1476 if (stm32port->port.mapbase == 0 || !stm32port->port.membase)
1482 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
1574 struct stm32_port *stm32port = container_of(port,
1577 clk_disable_unprepare(stm32port->clk);
1585 struct stm32_port *stm32port = container_of(port,
1588 return clk_prepare_enable(stm32port->clk);