Lines Matching refs:port
73 #define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
118 struct uart_port port;
171 return container_of(uart, struct sci_port, port);
176 * Common SCI definitions, dependent on the port's regshift
500 * value relative to the port mapping rather than the fixed offset
502 * register map for the given port.
534 if (!sci_port->port.dev)
537 pm_runtime_get_sync(sci_port->port.dev);
543 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
550 if (!sci_port->port.dev)
556 pm_runtime_put_sync(sci_port->port.dev);
559 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
563 * special-casing the port type, we check the port initialization
568 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
571 static void sci_start_tx(struct uart_port *port)
573 struct sci_port *s = to_sci_port(port);
577 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
578 u16 new, scr = serial_port_in(port, SCSCR);
584 serial_port_out(port, SCSCR, new);
587 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
594 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
596 ctrl = serial_port_in(port, SCSCR);
597 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
601 static void sci_stop_tx(struct uart_port *port)
606 ctrl = serial_port_in(port, SCSCR);
608 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
613 serial_port_out(port, SCSCR, ctrl);
616 if (to_sci_port(port)->chan_tx &&
617 !dma_submit_error(to_sci_port(port)->cookie_tx)) {
618 dmaengine_terminate_async(to_sci_port(port)->chan_tx);
619 to_sci_port(port)->cookie_tx = -EINVAL;
624 static void sci_start_rx(struct uart_port *port)
628 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
630 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
633 serial_port_out(port, SCSCR, ctrl);
636 static void sci_stop_rx(struct uart_port *port)
640 ctrl = serial_port_in(port, SCSCR);
642 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
645 ctrl &= ~port_rx_irq_mask(port);
647 serial_port_out(port, SCSCR, ctrl);
650 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
652 if (port->type == PORT_SCI) {
654 serial_port_out(port, SCxSR, mask);
655 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
658 serial_port_out(port, SCxSR,
659 serial_port_in(port, SCxSR) & mask);
662 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
670 static int sci_poll_get_char(struct uart_port *port)
676 status = serial_port_in(port, SCxSR);
677 if (status & SCxSR_ERRORS(port)) {
678 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
684 if (!(status & SCxSR_RDxF(port)))
687 c = serial_port_in(port, SCxRDR);
690 serial_port_in(port, SCxSR);
691 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
697 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
702 status = serial_port_in(port, SCxSR);
703 } while (!(status & SCxSR_TDxE(port)));
705 serial_port_out(port, SCxTDR, c);
706 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
711 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
713 struct sci_port *s = to_sci_port(port);
716 * Use port-specific handler if provided.
719 s->cfg->ops->init_pins(port, cflag);
723 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
724 u16 data = serial_port_in(port, SCPDR);
725 u16 ctrl = serial_port_in(port, SCPCR);
729 if (to_sci_port(port)->has_rtscts) {
731 if (!(port->mctrl & TIOCM_RTS)) {
744 serial_port_out(port, SCPDR, data);
745 serial_port_out(port, SCPCR, ctrl);
746 } else if (sci_getreg(port, SCSPTR)->size) {
747 u16 status = serial_port_in(port, SCSPTR);
751 if (!(port->mctrl & TIOCM_RTS))
757 serial_port_out(port, SCSPTR, status);
761 static int sci_txfill(struct uart_port *port)
763 struct sci_port *s = to_sci_port(port);
767 reg = sci_getreg(port, SCTFDR);
769 return serial_port_in(port, SCTFDR) & fifo_mask;
771 reg = sci_getreg(port, SCFDR);
773 return serial_port_in(port, SCFDR) >> 8;
775 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
778 static int sci_txroom(struct uart_port *port)
780 return port->fifosize - sci_txfill(port);
783 static int sci_rxfill(struct uart_port *port)
785 struct sci_port *s = to_sci_port(port);
789 reg = sci_getreg(port, SCRFDR);
791 return serial_port_in(port, SCRFDR) & fifo_mask;
793 reg = sci_getreg(port, SCFDR);
795 return serial_port_in(port, SCFDR) & fifo_mask;
797 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
804 static void sci_transmit_chars(struct uart_port *port)
806 struct circ_buf *xmit = &port->state->xmit;
807 unsigned int stopped = uart_tx_stopped(port);
812 status = serial_port_in(port, SCxSR);
813 if (!(status & SCxSR_TDxE(port))) {
814 ctrl = serial_port_in(port, SCSCR);
819 serial_port_out(port, SCSCR, ctrl);
823 count = sci_txroom(port);
828 if (port->x_char) {
829 c = port->x_char;
830 port->x_char = 0;
838 serial_port_out(port, SCxTDR, c);
840 port->icount.tx++;
843 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
846 uart_write_wakeup(port);
848 sci_stop_tx(port);
855 static void sci_receive_chars(struct uart_port *port)
857 struct tty_port *tport = &port->state->port;
862 status = serial_port_in(port, SCxSR);
863 if (!(status & SCxSR_RDxF(port)))
868 count = tty_buffer_request_room(tport, sci_rxfill(port));
874 if (port->type == PORT_SCI) {
875 char c = serial_port_in(port, SCxRDR);
876 if (uart_handle_sysrq_char(port, c))
884 if (port->type == PORT_SCIF ||
885 port->type == PORT_HSCIF) {
886 status = serial_port_in(port, SCxSR);
887 c = serial_port_in(port, SCxRDR);
889 c = serial_port_in(port, SCxRDR);
890 status = serial_port_in(port, SCxSR);
892 if (uart_handle_sysrq_char(port, c)) {
898 if (status & SCxSR_FER(port)) {
900 port->icount.frame++;
901 dev_notice(port->dev, "frame error\n");
902 } else if (status & SCxSR_PER(port)) {
904 port->icount.parity++;
905 dev_notice(port->dev, "parity error\n");
913 serial_port_in(port, SCxSR); /* dummy read */
914 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
917 port->icount.rx += count;
925 serial_port_in(port, SCxRDR);
926 serial_port_in(port, SCxSR); /* dummy read */
927 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
931 static int sci_handle_errors(struct uart_port *port)
934 unsigned short status = serial_port_in(port, SCxSR);
935 struct tty_port *tport = &port->state->port;
936 struct sci_port *s = to_sci_port(port);
940 port->icount.overrun++;
946 dev_notice(port->dev, "overrun error\n");
949 if (status & SCxSR_FER(port)) {
951 port->icount.frame++;
956 dev_notice(port->dev, "frame error\n");
959 if (status & SCxSR_PER(port)) {
961 port->icount.parity++;
966 dev_notice(port->dev, "parity error\n");
975 static int sci_handle_fifo_overrun(struct uart_port *port)
977 struct tty_port *tport = &port->state->port;
978 struct sci_port *s = to_sci_port(port);
983 reg = sci_getreg(port, s->params->overrun_reg);
987 status = serial_port_in(port, s->params->overrun_reg);
990 serial_port_out(port, s->params->overrun_reg, status);
992 port->icount.overrun++;
997 dev_dbg(port->dev, "overrun error\n");
1004 static int sci_handle_breaks(struct uart_port *port)
1007 unsigned short status = serial_port_in(port, SCxSR);
1008 struct tty_port *tport = &port->state->port;
1010 if (uart_handle_break(port))
1013 if (status & SCxSR_BRK(port)) {
1014 port->icount.brk++;
1020 dev_dbg(port->dev, "BREAK detected\n");
1026 copied += sci_handle_fifo_overrun(port);
1031 static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1035 if (rx_trig >= port->fifosize)
1036 rx_trig = port->fifosize - 1;
1041 if (sci_getreg(port, HSRTRGR)->size) {
1042 serial_port_out(port, HSRTRGR, rx_trig);
1046 switch (port->type) {
1083 serial_port_out(port, SCFCR,
1084 (serial_port_in(port, SCFCR) &
1090 static int scif_rtrg_enabled(struct uart_port *port)
1092 if (sci_getreg(port, HSRTRGR)->size)
1093 return serial_port_in(port, HSRTRGR) != 0;
1095 return (serial_port_in(port, SCFCR) &
1102 struct uart_port *port = &s->port;
1104 dev_dbg(port->dev, "Rx timed out\n");
1105 scif_set_rtrg(port, 1);
1111 struct uart_port *port = dev_get_drvdata(dev);
1112 struct sci_port *sci = to_sci_port(port);
1121 struct uart_port *port = dev_get_drvdata(dev);
1122 struct sci_port *sci = to_sci_port(port);
1130 sci->rx_trigger = scif_set_rtrg(port, r);
1131 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1132 scif_set_rtrg(port, 1);
1143 struct uart_port *port = dev_get_drvdata(dev);
1144 struct sci_port *sci = to_sci_port(port);
1147 if (port->type == PORT_HSCIF)
1160 struct uart_port *port = dev_get_drvdata(dev);
1161 struct sci_port *sci = to_sci_port(port);
1169 if (port->type == PORT_HSCIF) {
1175 scif_set_rtrg(port, 1);
1190 struct uart_port *port = &s->port;
1191 struct circ_buf *xmit = &port->state->xmit;
1194 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1196 spin_lock_irqsave(&port->lock, flags);
1201 port->icount.tx += s->tx_dma_len;
1204 uart_write_wakeup(port);
1211 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1212 u16 ctrl = serial_port_in(port, SCSCR);
1213 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1217 spin_unlock_irqrestore(&port->lock, flags);
1220 /* Locking: called with port lock held */
1223 struct uart_port *port = &s->port;
1224 struct tty_port *tport = &port->state->port;
1229 port->icount.buf_overrun++;
1231 port->icount.rx += copied;
1280 struct uart_port *port = &s->port;
1283 /* Direct new serial port interrupts back to CPU */
1284 scr = serial_port_in(port, SCSCR);
1285 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1289 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1296 struct uart_port *port = &s->port;
1301 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1304 spin_lock_irqsave(&port->lock, flags);
1313 tty_flip_buffer_push(&port->state->port);
1331 spin_unlock_irqrestore(&port->lock, flags);
1332 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1337 spin_unlock_irqrestore(&port->lock, flags);
1338 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1340 spin_lock_irqsave(&port->lock, flags);
1344 spin_unlock_irqrestore(&port->lock, flags);
1363 struct uart_port *port = &s->port;
1393 spin_lock_irqsave(&port->lock, flags);
1397 sci_start_rx(port);
1399 spin_unlock_irqrestore(&port->lock, flags);
1408 struct uart_port *port = &s->port;
1409 struct circ_buf *xmit = &port->state->xmit;
1418 * transmit till the end, and then the rest. Take the port lock to get a
1421 spin_lock_irq(&port->lock);
1430 spin_unlock_irq(&port->lock);
1438 spin_unlock_irq(&port->lock);
1439 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1450 spin_unlock_irq(&port->lock);
1451 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1455 spin_unlock_irq(&port->lock);
1456 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1463 spin_lock_irqsave(&port->lock, flags);
1465 sci_start_tx(port);
1466 spin_unlock_irqrestore(&port->lock, flags);
1474 struct uart_port *port = &s->port;
1481 dev_dbg(port->dev, "DMA Rx timed out\n");
1483 spin_lock_irqsave(&port->lock, flags);
1487 spin_unlock_irqrestore(&port->lock, flags);
1493 spin_unlock_irqrestore(&port->lock, flags);
1494 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1511 spin_unlock_irqrestore(&port->lock, flags);
1512 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1523 tty_flip_buffer_push(&port->state->port);
1526 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1531 spin_unlock_irqrestore(&port->lock, flags);
1536 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1543 chan = dma_request_slave_channel(port->dev,
1546 dev_dbg(port->dev, "dma_request_slave_channel failed\n");
1553 cfg.dst_addr = port->mapbase +
1554 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1557 cfg.src_addr = port->mapbase +
1558 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1564 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1572 static void sci_request_dma(struct uart_port *port)
1574 struct sci_port *s = to_sci_port(port);
1577 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1583 if (uart_console(port))
1586 if (!port->dev->of_node)
1595 if (!of_find_property(port->dev->of_node, "dmas", NULL))
1598 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1599 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1603 port->state->xmit.buf,
1607 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1610 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1612 port->state->xmit.buf, &s->tx_dma_addr);
1619 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1620 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1626 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1630 dev_warn(port->dev,
1653 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1658 static void sci_free_dma(struct uart_port *port)
1660 struct sci_port *s = to_sci_port(port);
1668 static void sci_flush_buffer(struct uart_port *port)
1670 struct sci_port *s = to_sci_port(port);
1684 static inline void sci_request_dma(struct uart_port *port)
1688 static inline void sci_free_dma(struct uart_port *port)
1697 struct uart_port *port = ptr;
1698 struct sci_port *s = to_sci_port(port);
1702 u16 scr = serial_port_in(port, SCSCR);
1703 u16 ssr = serial_port_in(port, SCxSR);
1706 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1715 serial_port_out(port, SCSCR, scr);
1717 serial_port_out(port, SCxSR,
1718 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1719 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1730 if (!scif_rtrg_enabled(port))
1731 scif_set_rtrg(port, s->rx_trigger);
1741 sci_receive_chars(port);
1748 struct uart_port *port = ptr;
1751 spin_lock_irqsave(&port->lock, flags);
1752 sci_transmit_chars(port);
1753 spin_unlock_irqrestore(&port->lock, flags);
1760 struct uart_port *port = ptr;
1763 sci_handle_breaks(port);
1766 serial_port_in(port, SCxRDR);
1768 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1775 struct uart_port *port = ptr;
1776 struct sci_port *s = to_sci_port(port);
1780 unsigned short ssr_status = serial_port_in(port, SCxSR);
1783 if (ssr_status & SCxSR_BRK(port))
1787 if (!(ssr_status & SCxSR_ERRORS(port)))
1792 if (port->type == PORT_SCI) {
1793 if (sci_handle_errors(port)) {
1795 serial_port_in(port, SCxSR);
1796 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1799 sci_handle_fifo_overrun(port);
1801 sci_receive_chars(port);
1804 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1816 struct uart_port *port = ptr;
1817 struct sci_port *s = to_sci_port(port);
1820 ssr_status = serial_port_in(port, SCxSR);
1821 scr_status = serial_port_in(port, SCSCR);
1824 else if (sci_getreg(port, s->params->overrun_reg)->size)
1825 orer_status = serial_port_in(port, s->params->overrun_reg);
1827 err_enabled = scr_status & port_rx_irq_mask(port);
1830 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1838 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1843 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1848 (ssr_status & SCxSR_BRK(port)) && err_enabled)
1853 sci_handle_fifo_overrun(port);
1906 static int sci_request_irq(struct sci_port *port)
1908 struct uart_port *up = &port->port;
1917 if (port->irqs[w] == port->irqs[i])
1922 if (SCIx_IRQ_IS_MUXED(port)) {
1926 irq = port->irqs[i];
1929 * Certain port types won't support all of the
1937 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1939 if (!port->irqstr[j]) {
1945 port->irqstr[j], port);
1956 free_irq(port->irqs[i], port);
1960 kfree(port->irqstr[j]);
1965 static void sci_free_irq(struct sci_port *port)
1974 int irq = port->irqs[i];
1977 * Certain port types won't support all of the available
1985 if (port->irqs[j] == irq)
1990 free_irq(port->irqs[i], port);
1991 kfree(port->irqstr[i]);
1993 if (SCIx_IRQ_IS_MUXED(port)) {
2000 static unsigned int sci_tx_empty(struct uart_port *port)
2002 unsigned short status = serial_port_in(port, SCxSR);
2003 unsigned short in_tx_fifo = sci_txfill(port);
2005 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
2008 static void sci_set_rts(struct uart_port *port, bool state)
2010 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2011 u16 data = serial_port_in(port, SCPDR);
2018 serial_port_out(port, SCPDR, data);
2021 serial_port_out(port, SCPCR,
2022 serial_port_in(port, SCPCR) | SCPCR_RTSC);
2023 } else if (sci_getreg(port, SCSPTR)->size) {
2024 u16 ctrl = serial_port_in(port, SCSPTR);
2031 serial_port_out(port, SCSPTR, ctrl);
2035 static bool sci_get_cts(struct uart_port *port)
2037 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2039 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
2040 } else if (sci_getreg(port, SCSPTR)->size) {
2042 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
2050 * CTS/RTS is supported in hardware by at least one port and controlled
2057 * port types, but not others. For these it's sufficient to test for the
2058 * existence of the support register and simply ignore the port type.
2060 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
2062 struct sci_port *s = to_sci_port(port);
2070 reg = sci_getreg(port, SCFCR);
2072 serial_port_out(port, SCFCR,
2073 serial_port_in(port, SCFCR) |
2084 serial_port_out(port, SCFCR,
2085 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
2088 sci_set_rts(port, 0);
2090 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2092 serial_port_out(port, SCPCR,
2093 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
2097 serial_port_out(port, SCFCR,
2098 serial_port_in(port, SCFCR) | SCFCR_MCE);
2101 sci_set_rts(port, 1);
2105 static unsigned int sci_get_mctrl(struct uart_port *port)
2107 struct sci_port *s = to_sci_port(port);
2118 if (sci_get_cts(port))
2131 static void sci_enable_ms(struct uart_port *port)
2133 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2136 static void sci_break_ctl(struct uart_port *port, int break_state)
2141 /* check wheter the port has SCSPTR */
2142 if (!sci_getreg(port, SCSPTR)->size) {
2150 spin_lock_irqsave(&port->lock, flags);
2151 scsptr = serial_port_in(port, SCSPTR);
2152 scscr = serial_port_in(port, SCSCR);
2162 serial_port_out(port, SCSPTR, scsptr);
2163 serial_port_out(port, SCSCR, scscr);
2164 spin_unlock_irqrestore(&port->lock, flags);
2167 static int sci_startup(struct uart_port *port)
2169 struct sci_port *s = to_sci_port(port);
2172 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2174 sci_request_dma(port);
2178 sci_free_dma(port);
2185 static void sci_shutdown(struct uart_port *port)
2187 struct sci_port *s = to_sci_port(port);
2191 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2194 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2196 spin_lock_irqsave(&port->lock, flags);
2197 sci_stop_rx(port);
2198 sci_stop_tx(port);
2203 scr = serial_port_in(port, SCSCR);
2204 serial_port_out(port, SCSCR, scr &
2206 spin_unlock_irqrestore(&port->lock, flags);
2210 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2211 port->line);
2219 sci_free_dma(port);
2229 if (s->port.type != PORT_HSCIF)
2244 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2256 if (s->port.type != PORT_HSCIF)
2275 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2289 if (s->port.type != PORT_HSCIF)
2343 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2348 static void sci_reset(struct uart_port *port)
2352 struct sci_port *s = to_sci_port(port);
2354 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
2356 reg = sci_getreg(port, SCFCR);
2358 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2360 sci_clear_SCxSR(port,
2361 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2362 SCxSR_BREAK_CLEAR(port));
2363 if (sci_getreg(port, SCLSR)->size) {
2364 status = serial_port_in(port, SCLSR);
2366 serial_port_out(port, SCLSR, status);
2371 scif_set_rtrg(port, 1);
2374 if (port->type == PORT_SCIFA ||
2375 port->type == PORT_SCIFB)
2376 scif_set_rtrg(port, 1);
2378 scif_set_rtrg(port, s->rx_trigger);
2383 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2389 struct sci_port *s = to_sci_port(port);
2410 * earlyprintk comes here early on with port->uartclk set to zero.
2417 if (!port->uartclk) {
2418 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2425 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2435 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2436 port->type != PORT_SCIFB) {
2450 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2466 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2494 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2503 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2504 serial_port_out(port, SCDL, dl);
2505 serial_port_out(port, SCCKS, sccks);
2508 spin_lock_irqsave(&port->lock, flags);
2510 sci_reset(port);
2512 uart_update_timeout(port, termios->c_cflag, baud);
2536 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2548 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2549 serial_port_out(port, SCSMR, smr_val);
2550 serial_port_out(port, SCBRR, brr);
2551 if (sci_getreg(port, HSSRR)->size) {
2572 serial_port_out(port, HSSRR, hssrr);
2580 smr_val |= serial_port_in(port, SCSMR) &
2582 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2583 serial_port_out(port, SCSMR, smr_val);
2586 sci_init_pins(port, termios->c_cflag);
2588 port->status &= ~UPSTAT_AUTOCTS;
2590 reg = sci_getreg(port, SCFCR);
2592 unsigned short ctrl = serial_port_in(port, SCFCR);
2594 if ((port->flags & UPF_HARD_FLOW) &&
2597 port->status |= UPSTAT_AUTOCTS;
2609 serial_port_out(port, SCFCR, ctrl);
2611 if (port->flags & UPF_HARD_FLOW) {
2613 sci_set_mctrl(port, port->mctrl);
2618 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2620 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2648 sci_start_rx(port);
2650 spin_unlock_irqrestore(&port->lock, flags);
2654 if (UART_ENABLE_MS(port, termios->c_cflag))
2655 sci_enable_ms(port);
2658 static void sci_pm(struct uart_port *port, unsigned int state,
2661 struct sci_port *sci_port = to_sci_port(port);
2673 static const char *sci_type(struct uart_port *port)
2675 switch (port->type) {
2693 static int sci_remap_port(struct uart_port *port)
2695 struct sci_port *sport = to_sci_port(port);
2700 if (port->membase)
2703 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2704 port->membase = ioremap(port->mapbase, sport->reg_size);
2705 if (unlikely(!port->membase)) {
2706 dev_err(port->dev, "can't remap port#%d\n", port->line);
2715 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2721 static void sci_release_port(struct uart_port *port)
2723 struct sci_port *sport = to_sci_port(port);
2725 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2726 iounmap(port->membase);
2727 port->membase = NULL;
2730 release_mem_region(port->mapbase, sport->reg_size);
2733 static int sci_request_port(struct uart_port *port)
2736 struct sci_port *sport = to_sci_port(port);
2739 res = request_mem_region(port->mapbase, sport->reg_size,
2740 dev_name(port->dev));
2742 dev_err(port->dev, "request_mem_region failed.");
2746 ret = sci_remap_port(port);
2755 static void sci_config_port(struct uart_port *port, int flags)
2758 struct sci_port *sport = to_sci_port(port);
2760 port->type = sport->cfg->type;
2761 sci_request_port(port);
2765 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2880 * where this particular port layout originated. This
2890 pr_err("Can't probe register map for given port\n");
2901 struct uart_port *port = &sci_port->port;
2908 port->ops = &sci_uart_ops;
2909 port->iotype = UPIO_MEM;
2910 port->line = index;
2911 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE);
2917 port->mapbase = res->start;
2928 * The fourth interrupt on SCI port is transmit end interrupt, so
2990 port->dev = &dev->dev;
2995 port->type = p->type;
2996 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
2997 port->fifosize = sci_port->params->fifosize;
2999 if (port->type == PORT_SCI && !dev->dev.of_node) {
3001 port->regshift = 2;
3003 port->regshift = 1;
3007 * The UART port needs an IRQ value, so we peg this to the RX IRQ
3013 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
3014 port->irqflags = 0;
3016 port->serial_in = sci_serial_in;
3017 port->serial_out = sci_serial_out;
3022 static void sci_cleanup_single(struct sci_port *port)
3024 pm_runtime_disable(port->port.dev);
3029 static void serial_console_putchar(struct uart_port *port, int ch)
3031 sci_poll_put_char(port, ch);
3035 * Print a string to the serial port trying not to disturb
3036 * any possible real use of the port...
3042 struct uart_port *port = &sci_port->port;
3047 if (port->sysrq)
3050 locked = spin_trylock_irqsave(&port->lock, flags);
3052 spin_lock_irqsave(&port->lock, flags);
3055 ctrl = serial_port_in(port, SCSCR);
3059 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
3061 uart_console_write(port, s, count, serial_console_putchar);
3064 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
3065 while ((serial_port_in(port, SCxSR) & bits) != bits)
3069 serial_port_out(port, SCSCR, ctrl);
3072 spin_unlock_irqrestore(&port->lock, flags);
3078 struct uart_port *port;
3092 port = &sci_port->port;
3097 if (!port->ops)
3100 ret = sci_remap_port(port);
3107 return uart_set_options(port, co, baud, parity, bits, flow);
3178 struct sci_port *port = platform_get_drvdata(dev);
3179 unsigned int type = port->port.type; /* uart_remove_... clears it */
3181 sci_ports_in_use &= ~BIT(port->port.line);
3182 uart_remove_one_port(&sci_uart_driver, &port->port);
3184 sci_cleanup_single(port);
3186 if (port->port.fifosize > 1)
3293 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3316 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3326 sciport->port.flags |= UPF_HARD_FLOW;
3329 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3376 if (sp->port.fifosize > 1) {
3381 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3382 sp->port.type == PORT_HSCIF) {
3385 if (sp->port.fifosize > 1) {
3406 uart_suspend_port(&sci_uart_driver, &sport->port);
3416 uart_resume_port(&sci_uart_driver, &sport->port);
3458 if (!device->port.membase)
3461 device->port.serial_in = sci_serial_in;
3462 device->port.serial_out = sci_serial_out;
3463 device->port.type = type;
3464 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3468 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3469 sci_serial_out(&sci_ports[0].port, SCSCR,